cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
dpaul24
Scholar
Scholar
13,141 Views
Registered: ‎08-07-2014

Is the VHDL 'div' operator synthesizable by Vivado2015.4

Jump to solution

Hello,

 

I want to use the VHDL div operator (/) in my RTL.

 

It will be something like

loop_value_int <= some_integer_value/32;

 

loop_value_int and some_integer_value will be declared as signals of type integer having a fixed range.

I have no problem if the result of the division is rounded down.

e.g. 44/32 = 1.375. I am only interested in the value 1, .375 is no use to me.

 

If the use the above, will I face a problem later during synthesis?

Target dev board is  Artix 701. 

 

Thanks.

 

 

 

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

0 Kudos
1 Solution

Accepted Solutions
balkris
Xilinx Employee
Xilinx Employee
19,293 Views
Registered: ‎08-01-2008

Yes you can use left **bleep** for division by for other division you can also use divider core

www.xilinx.com/support/documentation/ip_documentation/div_gen_ds530.pdf

/ is vhdl operator for division it should synthesis correctly by tool.

Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

View solution in original post

0 Kudos
5 Replies
zdzlin
Observer
Observer
13,131 Views
Registered: ‎09-25-2014

    If you just need to div a operator with the number of a power of 2, i.e, 2,4,8,16 and so on,you'd

better use the shoft operation instead of the divide, since divide is always the last choice in digital signal

processing

0 Kudos
dpaul24
Scholar
Scholar
13,124 Views
Registered: ‎08-07-2014

yes, my some_integer_value will always be an integer, such that 2**n = some_integer_value.

 

I would still like to use the / operator and so question regarding its synth remains the same.

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

0 Kudos
balkris
Xilinx Employee
Xilinx Employee
19,294 Views
Registered: ‎08-01-2008

Yes you can use left **bleep** for division by for other division you can also use divider core

www.xilinx.com/support/documentation/ip_documentation/div_gen_ds530.pdf

/ is vhdl operator for division it should synthesis correctly by tool.

Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

View solution in original post

0 Kudos
dpaul24
Scholar
Scholar
12,955 Views
Registered: ‎08-07-2014

Hello,

 

Division by 16. It will always remain fixed.

 

Part 1 =============================================================================

Please confirm if the following RTL will synthesize. I am concerned about the "/" operator.

Can I expect any latency on the signal where / is used?

My pak_clk_i = 125MHz. 

 

 

 signal frame_length_reg     : std_logic_vector (13 downto 0);
.
.
signal pak_len_words        : integer range 0 to 1023; 
.
.
.
  process (pak_clk_i) 
  begin 
    if rising_edge(pak_clk_i) then
      if pak_rst_n_i = '0' then 
        pak_len_words <= 0; 
      else 
        if rx_stats_valid_5q = '1' then 
          pak_len_words <= (to_integer(unsigned(frame_length_reg))+12)/16;
        else 
          pak_len_words <= pak_len_words; 
        end if;     
      end if; 
    end if;    
  end process;

 --------------------------------------------------------------

 

Part 2 =============================================================================

 

Will I get a performance gain if instead of using "/" operator, I shift data left 4 times, i.e. dividing by 16 or 2^4?

 

Which one is better to use? Saving clock cycles is my priority!

 

Regards,

dpaul

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

0 Kudos
u4223374
Advisor
Advisor
12,934 Views
Registered: ‎04-26-2015

For constant power-of-two division, Vivado will automatically convert "/" into a shift or bit-select operation. Both are effectively free in terms of logic and time.

0 Kudos