03-26-2015 12:55 PM
In synthesis step, I always find that there are "Macro" models, such as "16-bit Adder". Is it a Soft Macro built in Xilinx?
For example, I have an adder module like this:
module XADDER( input [15:0] A, input [15:0] B, output [15:0] OUT ); assign OUT = A + B; endmodule
In synthesis report, it shows this:
========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit <XADDER>. Related source file is "c:/users/leo/desktop/XADDER.v". Found 16-bit adder for signal <OUT> created at line 6. Summary: inferred 1 Adder/Subtractor(s). Unit <XADDER> synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 16-bit adder : 1
Then...Is there Soft Macro in Synthesis step?
If so, can we create one, our own soft macro?
Kudos are coming~
03-27-2015 08:44 AM
The Xilinx tools are inferring an adder. See the Synthesis guide for details (UG901).
You can create your own implementation of an adder - in fact you already have. You created "XADDER", and you filled it in with an inferred adder. You can replace that inferred adder with whatever you wish.
Perhaps you can detail a bit more what specifically you're trying to do? You have a succesful design now - what more are you trying to accomplish?
03-28-2015 04:18 PM
Thanks for help.
Actually, I am trying to design a fast adder which would beat Xilinx "inferred" adders in terms of delay. It is possible in theortical level, because the Xilinx inferred adder is a slow Ripple Carry Adder (RCA) which propagates the carry from LSB to MSB, and the Carry Lookahead Adder (CLA) , for example, computes the carry in parrallel which is far more quicker than Ripple Carry Adder.
The question is that -- what is true in theortical level is not always true in Xilinx Synthesis. The synthesis report shows that the Xilinx inferred adder is always the fastest adder among all of my fast adder design, such as CLA. The possible reason might be the routings. Xilinx inferred adder, the Macro one, always gets a perfect routing delay of below 42%, while my design, not a Macro, often gets a terrible routing delay of 90%+ in synthesis level.
So I am just wondering that if my design can be packaged into a Macro which can be inferred, can my adders reach a higher speed, even beat Xilinx inferred one?
03-29-2015 07:08 PM
So, two things...
First - you will not beat the Xilinx adder. While the Xilinx adder is conceptually represented as a ripple carry, it isn't - it is in fact a 4 bit carry look-ahead (8 bit in Ultrascale) with ripple carry between the 4 bit carry look-ahead units.
So, while theoretically you can do better with a fuller carry look-ahead, you won't. The reason is that these carry look-ahead units are hard coded in ASIC gates in the CLB, and are wired with dedicated nets between them. Nothing you can do in the fabric of the FPGA (using LUTs and general routing) is going to beat this (except maybe in some degenerate cases).
Given that the Xilinx carry chains are faster than pretty much anything else in the FPGA, Xilinx has made no mechanism for inferring addition using any structure other than the dedicated carry chains in the CLBs (with the exceptions of degenerately small adders [the threshold is set by synthesis, but is around 4 bits], which are mapped to a small number of LUTs instead).
The message in the synthesis log is during the elaboration stage which is simply stating that it recognized your coding style in HDL as an adder. This will be mapped to the carry chain.
03-30-2015 05:22 PM
And to answer generically the second part of your question: Can you "infer" your own "Soft Macros?"
The short answer - No, not really. The Xilinx synthesis guide explicity lists all coding styles, and what is inferred per each. These are set by the tools and not changeable by the user.
Can you get at what you want another way? Of course. Creating your own parameterized design, and instanciating it where needed, with the parameter overrides, and perhaps tie-off as neccesary.
Many users create their own set of "shared modules" (That's my term; "soft macro" has historical usage that may confuse things IMHO). These shared modules can be utilized on many FPGAs (or mutiple times on the same FPGA), with varied configurations. These can include FIFOs, synchronizers, timing generators, FIRs, FFTs, etc.. Most users don't bother with adders, for reasons that Avrum noted above.