11-24-2018 11:38 PM
I have a constant that I use to dictate whether I am testing or not. I have an entity that is only used for validation during testing. Instead of commenting it out over and over so that vivado doesn't waste time going through it during synthesis, only to realize that it isn't used, is there any syntactical VHDL magic that can be used to do something like the code below is implying?
if testing_is_going_on then some_entity: entity work.some_entity port map( clk => clk, a => a, b => b, c => c ); end if;
11-25-2018 12:27 AM
Oh, it is called an 'if generate'.
some_label: if testing_is_going_on generate some_entity: entity work.some_entity port map( clk => clk, a => a, b => b, c => c ); end generate some_label;