Is there any errors in my logic？Please help me?

[463717263]

This is my code ,

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:36:21 12/20/2013
// Design Name:
// Module Name: sram_ctr
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sram_ctr(
clk,
rst,
oe0,
we0,
ce0,
we1,
oe1,
ce1,
addr0,
addr1,
data0,
data1,
sram_din,
sram_dout,
sram_din_en,
sram_dout_en
);

input clk,rst,sram_din_en,sram_dout_en;

input [31:0] sram_din;
inout [31:0] data0,data1;

output [18:0] addr0,addr1;
output oe0,we0,ce0,oe1,we1,ce1;
output [31:0]sram_dout;

reg [18:0] addr0_rd,addr1_rd,addr0_wr,addr1_wr;
wire rd0,wr0,rd1,wr1,clk_n;
reg sram_sel;
reg rd0_empty,rd1_empty;
reg sram_dout;

//assign clk_n = ~clk;

always @(negedge clk or negedge rst)
begin
if (!rst)
begin
sram_sel <= 0;
end
else
begin
if (wr1 == 0 && addr1_wr == 19'd5) sram_sel <= ~sram_sel;
if (wr0 == 0 && addr0_wr == 19'd5) sram_sel <= ~sram_sel; 
end
end

assign rd0 = sram_sel; //当rd0=0，读SRAM0
assign wr1 = sram_sel; //当wr1=0,写SRAM1
assign rd1 = ~sram_sel; //当rd1=0，读SRAM1
assign wr0 = ~sram_sel; //当wr0=0，写SRAM0

assign ce0 = 0;
assign oe0 = clk || rd0;//clk_n || rd0; 
assign we0 = clk || wr0; 
assign addr0 = rd0 ? addr0_wr : addr0_rd;
assign data0 = (wr0 && sram_din_en) ? 19'hzzzzz : sram_din;

assign ce1 = 0;
assign oe1 = clk || rd1;//clk_n || rd1; 
assign we1 = clk || wr1; 
assign addr1 = rd1 ? addr1_wr : addr1_rd;
assign data1 = (wr1 && sram_din_en) ? 19'hzzzzz : sram_din;

assign sram_dout_reg = sram_sel ? data0 : data1;
always @ (negedge clk)
begin
if (sram_dout_en == 1)
begin
sram_dout <= sram_dout_reg;
end
end

always @(negedge clk/*clk_n*/ or negedge rst)
begin
if (!rst)
begin
rd0_empty <= 1;
rd1_empty <= 1;
end
else begin
if (addr0_rd == 19'd5) rd0_empty <= 0;
else if (wr0 == 0) rd0_empty <= 1;

if (addr1_rd == 19'd5) rd1_empty <= 0;
else if (wr1 == 0) rd1_empty <= 1;

end
end

always @ (negedge /*clk_n*/clk or negedge rst)
begin
if (!rst)
begin
addr0_rd <= 0;
addr1_rd <= 0;
end
else
begin
if (rd0 == 0 && rd0_empty == 1)
begin
addr0_rd <= addr0_rd + 1;
end
if (rd1 == 0 && rd1_empty == 1)
begin
addr1_rd <= addr1_rd + 1;
end
end
end

always @ (negedge clk or negedge rst)
begin
if (!rst)
begin
addr0_wr <= 0;
addr1_wr <= 0;
end
else
begin
if (wr0 == 0)
begin
addr0_wr <= addr0_wr + 1;
end
if (wr1 == 0)
begin
addr1_wr <= addr1_wr + 1;
end
end
end

endmodule

this is my Parametric Results Figure~

and why there is no conversion to come over for the second time.

thanks !

micheal~

[eteam00]

Micheal,

Here are some suggestions when soliciting assistance:

1.  When posting code, format your code for readability, 100 lines of code without indents and without comments is very difficult to read and understand.  You would be requiring every reader to manually re-format and edit your code for the privilege of assisting you.  There are FAQs for new users which provide help for formattng posts with source code.

2.  Include comments in your source code to assist readers in understanding the intent of your code.

3. Describe the problem with which you seek help in detail.  For example: 'Is this right?' is a vague question, and is likely to provoke useless and incorrect answers.  Nor is "it doesn't work" a useful problem, without understanding specifically your expected results vs. your actual results.

Thank you for helping us to help you.

-- Bob Elkind

[463717263]

hi Bob:

sorry ! I think I should format my code and then ask for help!  

 Thanks for Reminding Me.

micheal

[463717263]

module sram_ctr(
								  clk,
								  rst,
								  oe0,
								  we0,
								  ce0,
								  we1,
								  oe1,
								  ce1,
								  addr0,
								  addr1,
								  data0,
								  data1,
								  sram_din,
								  sram_dout,
								  sram_din_en,
								  sram_dout_en
    );

input clk,rst,sram_din_en,sram_dout_en;

input [31:0] sram_din;
inout [31:0] data0,data1;

output [18:0] addr0,addr1;
output oe0,we0,ce0,oe1,we1,ce1;
output [31:0] sram_dout;

reg  [18:0] addr0_rd,addr1_rd,addr0_wr,addr1_wr;
wire rd0,wr0,rd1,wr1,clk_n;
reg  sram_sel;
reg  rd0_empty,rd1_empty;
reg  [31:0] sram_dout;

//assign clk_n = ~clk;

always @(negedge clk or negedge rst)
begin
	if (!rst) 
		begin
			sram_sel <= 0;
		end
	else 
		begin
			if (wr1 == 0 && addr1_wr == 19'd5) 	
				sram_sel <= ~sram_sel;
				addr1_wr <= 1;
 			if (wr0 == 0 && addr0_wr == 19'd5) 	
				sram_sel <= ~sram_sel;
				addr0_wr <= 1;				
		end
end


assign rd0 = sram_sel;  
assign wr1 = sram_sel;  
assign rd1 = ~sram_sel; 
assign wr0 = ~sram_sel; 


assign ce0 = 0;
assign oe0 = clk || rd0;//clk_n || rd0; 
assign we0 = clk || wr0; 
assign addr0 = rd0 ? addr0_wr : addr0_rd;
assign data0 = (wr0 && sram_din_en) ? 19'hzzzzz : sram_din;

assign ce1 = 0;
assign oe1 = clk || rd1;//clk_n || rd1; 
assign we1 = clk || wr1; 
assign addr1 = rd1 ? addr1_wr : addr1_rd;
assign data1 = (wr1 && sram_din_en) ? 19'hzzzzz : sram_din;

assign sram_dout_reg = sram_sel ? data0 : data1;
always @ (negedge clk)
begin
		if (sram_dout_en == 1)
			begin
				sram_dout <= sram_dout_reg;
			end
end

always @(negedge clk/*clk_n*/ or negedge rst)
begin
		if (!rst)
				begin 
					rd0_empty <= 1;
					rd1_empty <= 1;
				end
		else begin 
				if (addr0_rd == 19'd5) 	
					rd0_empty <= 0;
				else if  (wr0 == 0) 	   
					rd0_empty <= 1;
					addr0_rd <= 1;
				
				if (addr1_rd == 19'd5)  
					rd1_empty <= 0;
				else if  (wr1 == 0)		
					rd1_empty <= 1;
					addr1_rd <= 1;

			  end
end

always @ (negedge /*clk_n*/clk or negedge rst)
begin
	if (!rst)
		begin 
			addr0_rd <= 0;
			addr1_rd <= 0;
		end
	else
		begin
			if (rd0 == 0 && rd0_empty == 1)
				begin
					addr0_rd <= addr0_rd + 1;
				end
			if (rd1 == 0 && rd1_empty == 1)
				begin
					addr1_rd <= addr1_rd + 1;
				end
		end
end

always @ (negedge clk or negedge rst)
begin
	if (!rst)
		begin
			addr0_wr <= 0;
			addr1_wr <= 0;
		end
	else
		begin
			if (wr0 == 0)
				begin 
					addr0_wr <= addr0_wr + 1;
				end
			if (wr1 == 0)
				begin
					addr1_wr <= addr1_wr + 1;
				end
		end
end

endmodule 

[eteam00]

What is your question or problem?

-- Bob Elkind

[bassman59]

Did you simulate this code, or are you asking the community to do it for you?