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Visitor davidrupe
Visitor
10,954 Views
Registered: ‎12-31-2013

Is there support for string parameters in SystemVerilog?

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 parameter string                 NAME = "UNIQUE_NAME",

 

[Synth 8-27] string type not supported ["my_file.sv":14]

 

If not, there should be!

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1 Solution

Accepted Solutions
Explorer
Explorer
18,697 Views
Registered: ‎09-07-2011

Re: Is there support for string parameters in SystemVerilog?

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If you need a work around, you can probably drop the "string" type, and do it classic verilog style:

 

parameter name = "UNIQUE_NAME";

    or

parameter [11*8:1] = "UNIQUE_NAME";

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6 Replies
Explorer
Explorer
18,698 Views
Registered: ‎09-07-2011

Re: Is there support for string parameters in SystemVerilog?

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If you need a work around, you can probably drop the "string" type, and do it classic verilog style:

 

parameter name = "UNIQUE_NAME";

    or

parameter [11*8:1] = "UNIQUE_NAME";

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Moderator
Moderator
10,898 Views
Registered: ‎01-16-2013

Re: Is there support for string parameters in SystemVerilog?

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@davidrupe

 

There is an existing CR(Change request)#951093 on Vivado synthesis to support SystemVerilog string type parameters.

This will be fixed in future releases of Vivado. Untill then you can use the Workaround of removing the string datatype, a string can still be used and is detected by Synthesis:

 

 parameter  NAME = "UNIQUE_NAME"; 

 

Regards,

Syed

 

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Visitor davidrupe
Visitor
10,864 Views
Registered: ‎12-31-2013

Re: Is there support for string parameters in SystemVerilog?

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Perfect, thanks guys.  I think the problem is I never actually used verilog much.  Straight from VHDL to SystemVerilog.  Didn't even think to remove the type...did think of the byte array though.

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2,725 Views
Registered: ‎07-18-2018

Re: Is there support for string parameters in SystemVerilog?

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What release will this be fixed in? As of 2018.2 it is still not fixed. My issue is the following:

 

#(

  parameter SZ,

  parameter string X[SZ]

)

 

If I leave "string" in there, Quartus and Modelsim are happy but Vivado isn't

If I take it out, Vivado is happy, but Modelsim isn't

Visitor sroche11
Visitor
1,141 Views
Registered: ‎09-06-2018

Re: Is there support for string parameters in SystemVerilog?

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Here is a workaround that worked for me, with parameter/localparam of type array of string :

`define _NO_SIM
//pragma translate_off
`undef _NO_SIM
//pragma translate_on

module module_name
#(
`ifdef _NO_SIM
parameter X[3] = '{"A","B","C"},
`else
parameter string X[3] = '{"A","B","C"},
`endif
...
)(
...
);

`ifdef _NO_SIM
localparam XX[3] = '{"AA","BB","CC"};
`else
localparam string XX[3] = '{"AA","BB","CC"};
`endif

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Xilinx Employee
Xilinx Employee
1,120 Views
Registered: ‎05-14-2008

Re: Is there support for string parameters in SystemVerilog?

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madelman@tower-research.com wrote:

What release will this be fixed in? As of 2018.2 it is still not fixed. My issue is the following:

 


It turned out string type will not be supported.

Please use the workarounds mentioned in this thread.

-vivian

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