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Participant
Participant
568 Views
Registered: ‎03-04-2019

Is this possible in VHDL?

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.numeric_std.all;

     :

     :

     :

var<=var SLL 2;

     :

     :

 

 

continue error : can't determine definition of operator ""sll"" -- found 0 possible definitions

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Xilinx Employee
Xilinx Employee
545 Views
Registered: ‎05-22-2018

Hi @ghkdkrtks ,

Try to set the fileset of the RTL file as VHDL 2008:

vhdlllllCapture.JPG

Thanks,

Raj

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Scholar
Scholar
510 Views
Registered: ‎08-01-2012

You dont show the declaration of var to show it's type, and you dont specify what language version you are using.

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Participant
Participant
442 Views
Registered: ‎03-04-2019

var  : in std_logic_vector(31 downto 0);

VHDL 2008=> the same result

 

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Teacher
Teacher
437 Views
Registered: ‎11-14-2011

There are no definitions for "sll" using std_logic_vector in the numeric_std library.

You will need to declare var as signed or unsigned.

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"That which we must learn to do, we learn by doing." - Aristotle
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Scholar
Scholar
427 Views
Registered: ‎08-01-2012

There are alternatives: use the numeric_std_unsigned library and either use the shift_left function or multiply by 2**N. These should result in the same logic as SLL:

var <= SHIFT_LEFT(var, 2);
var <= var * (2**2);
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