cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer
Observer
7,988 Views
Registered: ‎11-12-2008

Is this situation normal?

I found in the synthesis report a clock was generated for my FSM.Is this situation normal?Thanks!

 

I use ISE10.1 XST.

My FSM code is as below:

 

always @(posedge clk or negedge rst)
       if(~rst)  txstate<=IDLE;
       else  txstate<=txstate_next;

always @(*)
    case(txstate)
      IDLE:      if(~rdy0)         txstate_next<=LOADST;
                 else              txstate_next<=IDLE;
      LOADST:    if(loadst_done)   txstate_next<=LOADDATA;
                 else  
                 if(loadst_err)    txstate_next<=IDLE;
                 else              txstate_next<=LOADST; 
      LOADDATA:  if(loaddata_done) txstate_next<=CRC;
                 else
                 if(loaddata_err)  txstate_next<=IDLE;
                 else              txstate_next<=LOADDATA;
      CRC:       if(crc_done)      txstate_next<=SENDDATA;
                 else              txstate_next<=CRC;
      SENDDATA:  if(timeout)       txstate_next<=IDLE;
                 else
                 if(senddata_done) txstate_next<=PADDING;
                 else              txstate_next<=SENDDATA;
      PADDING:   if(done)          txstate_next<=IDLE;
                 else              txstate_next<=PADDING;
      default:   txstate_next<=IDLE;
      endcase

        

0 Kudos
13 Replies
Highlighted
Explorer
Explorer
7,980 Views
Registered: ‎07-27-2009

Re: Is this situation normal?

Not a joke, right?

 

You mean that the _sequential_ FSM generates a clock or that it needs a clock? The first always block infers your state registers and these seem to require a clock and a negedge reset, pretty conventional stuff that indeed uses a clock.

 

Cheers!

0 Kudos
Highlighted
Observer
Observer
7,959 Views
Registered: ‎11-12-2008

Re: Is this situation normal?

woutersj :sure,clk is the system clock and it is in the synthesis report.Besides clk,a new clock was generated named  rxstate_FSM_FFd2.

But I didn't use any other signal as a clock in the code.Why?

                

0 Kudos
Highlighted
Historian
Historian
7,940 Views
Registered: ‎02-25-2008

Re: Is this situation normal?


jason_1997 wrote:

woutersj :sure,clk is the system clock and it is in the synthesis report.Besides clk,a new clock was generated named  rxstate_FSM_FFd2.

But I didn't use any other signal as a clock in the code.Why?

                


The code snippet you posted makes no mention of a signal called rxstate (which I assume is the state register for the receiver machine).

----------------------------Yes, I do this for a living.
0 Kudos
Highlighted
Observer
Observer
7,924 Views
Registered: ‎11-12-2008

Re: Is this situation normal?

sorry, a spelling mistake.it should be   txstate_FSM_FFd2

just now I tried again and found the gated clock was generated when the length of the frame is a variable.

when the frame's length is fixed,no gated clock was generated.

why? 

0 Kudos
Highlighted
Historian
Historian
7,917 Views
Registered: ‎02-25-2008

Re: Is this situation normal?


jason_1997 wrote:

sorry, a spelling mistake.it should be   txstate_FSM_FFd2

just now I tried again and found the gated clock was generated when the length of the frame is a variable.

when the frame's length is fixed,no gated clock was generated.

why? 


So you need to tell us the name of this gated clock.

 

You're only showing us the state-transition part of your state machine, and it's one of those awful two-process machines. There is obviously something else (another always block?) that uses the state register to determine what to do next. And I suspect that this unknown (to us) logic has code that creates the SPI clock by doing something like

 

    spiclk <=  clk & enable;

 

and worse, you use spiclk as both the SPI clock output and as an internal FPGA clock.

 

-a

----------------------------Yes, I do this for a living.
0 Kudos
Highlighted
Observer
Observer
7,906 Views
Registered: ‎11-12-2008

Re: Is this situation normal?

The remaining part of the code are all something like "always@(posedge clk)  if(txstate == /onestate/)    signal<=value;"

 I didn't use combinational logic to generate a clock and there's no more clock in this code.

The only reason that caused the problem was the variable length of the frame.

Once this was set to be a constant,the gated clock didn't show up again. 

0 Kudos
Highlighted
Observer
Observer
7,905 Views
Registered: ‎11-12-2008

Re: Is this situation normal?

The name of the generated gated clock  is  txstate_FSM_FFd2.
0 Kudos
Highlighted
Historian
Historian
7,894 Views
Registered: ‎02-25-2008

Re: Is this situation normal?


jason_1997 wrote:

The remaining part of the code are all something like "always@(posedge clk)  if(txstate == /onestate/)    signal<=value;"

 I didn't use combinational logic to generate a clock and there's no more clock in this code.

The only reason that caused the problem was the variable length of the frame.

Once this was set to be a constant,the gated clock didn't show up again. 


without seeing the rest of the code it's impossible to determine what's going on.

 

Oh, and it appears that you have a three-process state machine (one combinatorial process for state transitions, a second process to register the state variable, and a third to update outputs based on the state). I suspect that this is the root of your problem -- sometimes the tools have a difficult time with that third process which decodes the states and updates the machine outputs.

 

Try re-writing the state machine using the synchronous single-process (always block) style.

----------------------------Yes, I do this for a living.
0 Kudos
Highlighted
Observer
Observer
7,857 Views
Registered: ‎11-12-2008

Re: Is this situation normal?

thanks, bassman

I'll try the other fsm coding styles but it seems a little difficult to use the one-process style because the output logic is a little complex...  

0 Kudos
Highlighted
Observer
Observer
4,440 Views
Registered: ‎11-12-2008

Re: Is this situation normal?

but,,,the three-process style works well and no gated clock is generated at all when I set the frame length to be a constant.

so,,maybe there're other reasons... 

0 Kudos
Highlighted
Historian
Historian
4,433 Views
Registered: ‎02-25-2008

Re: Is this situation normal?


jason_1997 wrote:

but,,,the three-process style works well and no gated clock is generated at all when I set the frame length to be a constant.

so,,maybe there're other reasons... 


Like I said, without seeing the code it is not possible to guess.

----------------------------Yes, I do this for a living.
0 Kudos
Highlighted
Historian
Historian
4,432 Views
Registered: ‎02-25-2008

Re: Is this situation normal?


jason_1997 wrote:

thanks, bassman

I'll try the other fsm coding styles but it seems a little difficult to use the one-process style because the output logic is a little complex...  


I don't know -- I've always found that using the one-process state machine makes my life a lot easier, even with complex output logic.

 

-a

----------------------------Yes, I do this for a living.
0 Kudos
Highlighted
Observer
Observer
4,425 Views
Registered: ‎11-12-2008

Re: Is this situation normal?

I'll try it.thanks!:)
0 Kudos