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Newbie a15420
Newbie
483 Views
Registered: ‎02-20-2013

Issue with syhtnesizing for the VU9P chip

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Hello everyone,

 

I am using the Vivado suite in a more niche context but i would like to see if anyone here might be able to give me any hints.

We are using Maxeler DFE cards that are Data-center boards that include a VU9 chip at their heart. The Board tool-flow calls the vivado suite when it comes to synthesising for the chip. In that point during building i get this error message from the external tool (vivado 2017.4 in this case).

[java] Tue 14:58: Generating input files (VHDL, netlists, vendor specific IP cores)
     [java] Tue 14:58: ERROR: Error running external tool :-
     [java] Tue 14:58: ERROR: Problem            : Error generating IP with Vivado: Errors reported in /home/maxeler/Workspace/

Numerics-chap03-example01-movingaverageexceptions-DFE/builds/Tutorial/MovingAverageExceptions_MAX5C_DFE/scratch/com_maxeler_platform_max5_toolchain_ip_fifogenerator_FifoGeneratorIp_vivado2017_4_xcVU9P_FLGB2104_2_E_34_512_34_forcebram_dualclock_rst_pf496_fwft/com_maxeler_platform_max5_toolchain_ip_fifogenerator_FifoGeneratorIp_vivado2017_4_xcVU9P_FLGB2104_2_E_34_512_34_forcebram_dualclock_rst_pf496_fwft_gen.log

 
It seems there is something missing from the lisencing but i have included in the lisence for the VU9P.
So i cannot understand what is missing.

This is the current lisence: https://imgur.com/Sxh4NlT

Any helpfull hints about what might be wrong is greately appreciated.

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1 Solution

Accepted Solutions
Newbie a15420
Newbie
328 Views
Registered: ‎02-20-2013

Re: Issue with syhtnesizing for the VU9P chip

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Hello,

In believe i found the issue in the log. The lisence was not pulled up correctly even though the lisence sever was running. It might be an issues of needing a more recent version of lmtools. I will try it out and update. 

View solution in original post

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5 Replies
Moderator
Moderator
449 Views
Registered: ‎07-21-2014

Re: Issue with syhtnesizing for the VU9P chip

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@a15420

Which tool you used to synthesize the design?
Can you please share the Vivado complete log here(if used).

Thanks
Anusheel 

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Newbie a15420
Newbie
418 Views
Registered: ‎02-20-2013

Re: Issue with syhtnesizing for the VU9P chip

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Hello Anusheel,

 

Sorry for the late reply.

 

This is what i get from the tool log. It is not the log directly from vivado bu the high level tool that calls vivado 2017.4: https://pastebin.com/315Rk7s7


The tool is Called maxIDE and it is made my the DFE board desingers.


Thank you for your time

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Xilinx Employee
Xilinx Employee
401 Views
Registered: ‎05-14-2008

Re: Issue with syhtnesizing for the VU9P chip

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Do you have this log file:

com_maxeler_platform_max5_toolchain_ip_fifogenerator_FifoGeneratorIp_vivado2017_4_xcVU9P_FLGB2104_2_E_34_512_34_forcebram_dualclock_rst_pf496_fwft_gen.log 

This seems to me the Vivado log file and it will provide more infor as to why it failed.

-vivian

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Newbie a15420
Newbie
329 Views
Registered: ‎02-20-2013

Re: Issue with syhtnesizing for the VU9P chip

Jump to solution

Hello,

In believe i found the issue in the log. The lisence was not pulled up correctly even though the lisence sever was running. It might be an issues of needing a more recent version of lmtools. I will try it out and update. 

View solution in original post

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Newbie a15420
Newbie
289 Views
Registered: ‎02-20-2013

Re: Issue with syhtnesizing for the VU9P chip

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turns out that indeed it was the flexlm version that was the problem. Using 11.14.1 actually allowed the build to complete normally. thank you for pointing me to the log
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