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Visitor
Visitor
657 Views
Registered: ‎03-01-2019

Keep original pin names in RTL Elaboration and Design Synthesis of an IP Block added in an IP Integrator Block Design

Hi,

I am designing a system composed of a Zynq processor connected to my own hardware IP. First, I create the Zynq in the IP Integrator Block Design and then add my IP with the "Create and Package New IP" tool. After I package my IP and come back to the main Vivado window I need to get access to the pins of the IP I have created. 

Why do I need that? Because I want to force '0' or '1' in all output bits of only my IP after implementing my design. To do that I must add a multiplexer to all output pins to be able to select the normal output or my forced value while application is running at my zedboard. I want to do that using a TCL script to automatically add a 2:1 Mux and reconnect everything to my zynq processor. I want to do it using script to allow the process automation for any IP I migth have with any number of outputs the IP might have.

The problem occurs because atfer I package my IP and come back to the main Vivado window, looks like the synthesis have flatenned my design, and I do not have my original output pins acessible anymore.

What I have already tried:

1. Set the flatten hierarchi to none: Did not help.

used the command: "set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY none [get_runs synth_1]"

2. Set the DONT_TOUCH property true: Created a synthesis constraint file with the command "set_property DONT_TOUCH true [get_cells -hierarchical -filter {!IS_PRIMITIVE && NAME =~ "*myip1*"}]" but did not change the result.

 

Any insights on what should I do?

Thank you for your help,

Regards,

Eduardo

 

 

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Xilinx Employee
Xilinx Employee
616 Views
Registered: ‎05-14-2008

How do you query those pins of the IP? 

E.g. at which stage do you run the get_pins command? In the implementated design?

How do you know that Vivado flatterned the hierarchies?

-vivian

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Highlighted
Visitor
Visitor
602 Views
Registered: ‎03-01-2019

Hi vivian, thank you for the reply.

After synthesis I click at my ip at the netlist tab and look at pins tab at the cell properties. The expected result should be the ports of my ip entity as presented in picture bellow, which was obtained when I run the synthesis after packaging the IP. 

Expected.PNG

But after I package my ip and go back to the main vivado window, after I run synthesis and check the same IP cell pins I get the following results, which is the same result as obtained after I set the flatten hierarchy to rebuilt in my IP editing. So, even if I set the flatten to none, the obtained cell pins looks like flattened.

Flattened.PNG

Hope I have cleared all your questions. Please let me know if I am missing something.

Regards,

Eduardo.

Expected.PNG
Flattened.PNG
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Xilinx Employee
Xilinx Employee
574 Views
Registered: ‎04-19-2010

How are you running your design with your IP?  Is this a full top down flow, or do you have OOC runs in your design? If the IP that you want to keep static is in one of those out of context runs, then putting flatten_hierarchy none on synth_1 will not work, you will need to put it on the OOC run in question.  I only ask because some of your hierarchy looks like it might come from an OOC run (design_1, U0...).

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Visitor
Visitor
558 Views
Registered: ‎03-01-2019

Hi, thanks for your reply.

I am following the tutorial "Creating a custom IP block in Vivado Using ZedBoard: A Tutorial". Available at :

http://islab.soe.uoguelph.ca/sareibi/TEACHING_dr/XILINX_VIVADO_dr/VivadoEmbeddedZyncTutorialAddIP.pdf

I am not sure if it is considered an OOC. What I do is to put the  flatten_hierarchy none on both, the IP creation and packaging vivado window and the main design window. When I am in the IP window and check the hierarchy it is not flattened but when I come back to the main window, where I need to run my script (as previously explained), the design is flattened. I also tried to run my script in the IP window but the modifications my script does in the design do not take place when I review and package my IP. 

I see two possible solutions here that I need help to implement:

1 - Make my IP not flattened from the main design context;

2 - Make my script changes to take effect in the IP design context;

Any other idea?

Thanks for your help.

Eduardo.

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