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nikolay
Visitor
Visitor
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Registered: ‎11-02-2009

LUT_MAP constraint for XST

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Hi,

 

I have problem with the synthesis constraint LUT_MAP for XST (ISE 10.1)

 

I want to force XST to map a combinatorial function that has 5 inputs and 2 outputs on a single LUT6_2 in Virtex5. I tried to do this by using VHDL attributes (as described in the XST User Guide)  in the following way:

 

entity myFUNC is
    port (
        -- 5 x In
        I0 : in  STD_LOGIC;    

        I1 : in  STD_LOGIC; 

        I3 : in  STD_LOGIC;    
        I4 : in  STD_LOGIC; 
        I5 : in  STD_LOGIC;  
        -- 2 x Out
        G   : out STD_LOGIC;   
        CXO : out STD_LOGIC 
    );

    --
    attribute LUT_MAP: string;
    attribute LUT_MAP of myFUNC : entity is "yes";
    --
end myFUNC ;

 

However, XST does not respond,and does not give any explanation for that. The best result I can get is 2 times LUT5.

 

I tried using synthesis constraint file (according to the XST User Guide):

 

MODEL "myFUNC" lut_map=yes;
MODEL "myFUNC" lut_map=yes;

 

The result was the same - XST does not respond to the constraint.

 

 

The third way I can try is to instantiate directly a LUT6_2 primitive, but I would like to avoid this, if possible.

 

 

 

Does anybody knows what could be the reason that XST does not obey the LUT_MAP constraint?

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blaine
Xilinx Employee
Xilinx Employee
6,015 Views
Registered: ‎04-11-2008

You should use the HLUTNM constraint. This will add a hierarchy name and allow you to reuse it more than once in a design.

 

John

 

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3 Replies
gszakacs
Professor
Professor
5,214 Views
Registered: ‎08-14-2007

I don't see the LUT_MAP constraint in the ISE 10.1 constraint guide.  Don't you want to

use the "LUTNM" constraint?

-- Gabor
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nikolay
Visitor
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5,211 Views
Registered: ‎11-02-2009

Hi ,

 

The LUT_MAP constraint I found here : http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/xst.pdf , page 338. It is a synthesis constraint, not a MAP or PAR constraint. 

 

Anyway, thanks for your suggestion. The LUTNM seams to be another option I didn't know about. However, it will require more effort - I have to identify all the pairs of LUT5 (they are many) and assign the same LUTNM name to each pair.

 

Regards 

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blaine
Xilinx Employee
Xilinx Employee
6,016 Views
Registered: ‎04-11-2008

You should use the HLUTNM constraint. This will add a hierarchy name and allow you to reuse it more than once in a design.

 

John

 

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