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Harish_Algat
Participant
Participant
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Registered: ‎06-04-2020

LUT on the clock path due to clock gating

In the design LUT is present in the clock path even if the gated_clock_conversion is allowed in the synthesis option and gated_clock = yes in the RTL still the LUT is present on the clock path 

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maps-mpls
Mentor
Mentor
378 Views
Registered: ‎06-20-2017

In this situation, I would manually instantiate a BUFGCE instead of using gated clock conversion.  Have you tried that?

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aschule
Xilinx Employee
Xilinx Employee
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Registered: ‎04-19-2010

What exactly is the functionality of that LUT?  If it is something like an AND gate, this looks like it would be some type of bug that should be fixed.  The synthesis tool should figure out any type of unary function and be able to ungate the clocks.  Are there any KEEP/DONT_TOUCH/KEEP_HIERARCHY attributes in the design that would prevent the clock conversion from happening?

 

Also, I agree with the previous post.  Instantiating your own clock tree is always a great way to make sure you get the exact clock tree that you want.

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