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Adventurer
Adventurer
1,242 Views
Registered: ‎01-26-2017

Large dual-port BRAM reads (Native) does not read every cycle

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Hi there,

 

I am having some trouble using BRAMs as 5 row buffers stuck together. I have dual port BRAM that is writing 14 bit data in on the A port, and reading out 448 bit data on the B port, which is constructed into a 5x5 kernel for later use. The issue I am having is that my reads should occur every cycle as the kernel "slides across" the row buffers, but the problem is that the output data changes only every 8 cycles. 

 

I have attached some screenshots to explain my design. Checking the screenshot, it is clear that my reading and writing should be done by incrementing by the size of my kernel (which is 5 in this case). I.e on first cycle, read_addr = 0, then on 2nd, read_addr = 5 etc.  

 

And then the waveform output does not change every cycle, however notice that the output is a zero matrix at address 40 as expected. This is very confusing to me, my wr_en and rd_en are constant on their respective ports, otherwise I would say this is just that my rd_en is being held low for 8 cycles etc or my din on the write port is held constant by accident. Does anyone have any ideas?

 

Thanks for your time.

--- Estimated Development time: 2*Pi*(planned completion date) ---
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memory structure.PNG
bram_reads.PNG
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Xilinx Employee
Xilinx Employee
1,463 Views
Registered: ‎05-14-2008

Since you've had a new post on that board, please close this thread by accepting an answer as solution. Thanks.

 

-vivian

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Xilinx Employee
Xilinx Employee
1,211 Views
Registered: ‎05-14-2008

The BRAM/FIFO board is more appropriate for your problem.

https://forums.xilinx.com/t5/BRAM-FIFO/bd-p/OTHERIP

 

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
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Adventurer
Adventurer
1,204 Views
Registered: ‎01-26-2017

Thanks, will report there

--- Estimated Development time: 2*Pi*(planned completion date) ---
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Highlighted
Xilinx Employee
Xilinx Employee
1,464 Views
Registered: ‎05-14-2008

Since you've had a new post on that board, please close this thread by accepting an answer as solution. Thanks.

 

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------

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