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Visitor
Visitor
1,493 Views
Registered: ‎10-26-2019

Limit ammount of input variables in a LUT

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When I synthesize a circuit onto a device it often uses all 6 or 4 inputs of the LUTs. However, I want to restrict that number to 2 or 3 inputs per LUT. Is there an option for that? If so, what option and how do I use it?

Thanks in advance

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-14-2018

Hi @apbianco ,

I tried your testcase and tool applied BLOCK SYNTH.MAX_LUT_INPUT property correctly.

This is already covered here in discussion, BLOCK_SYNTH properties are applied on hierarchical blocks and not on top level.

Attached is snapshot when MAX_LUT_INPUT property is applied with value as 4. Also attached testcase.

Thanks,

apetley

 

 

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BLOCK_SYNTH.JPG
17 Replies
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1,473 Views
Registered: ‎01-22-2015

@apbianco 

Welcome to the Xilinx Forum!

If you use a block synthesis strategy then you can prevent use of 5-input and 6-input LUTs using the MAX_LUT_INPUT option shown in Table 3-1 of UG901.  -not exactly what you wanted, but maybe helpful.

Mark

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Visitor
Visitor
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Registered: ‎10-26-2019

Ok, I tried doing that but I can't get it to work. The line I'm running is 

set_property BLOCK_SYNTH.MAX_LUT_INPUT 4 [get_cells]

right after synth_design command. However, it doesn't do anything upon inspection under the schematic viewer, it still uses the 6 LUT. Any ideas?

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Teacher
Teacher
1,369 Views
Registered: ‎07-09-2009

Sorry , this is not an answer ,

Im interested in what the advantage of resticting the number of inputs to a LUT is ..

  It had not even entered my head that there would be a means of doing it.. which there is, so I wonder why.

 

 

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1,355 Views
Registered: ‎09-17-2018

I would.

Go read up on the TCL commands.  I recall in architectual studies we targeted designs with various LUT sizes to see what fit best looking at future devices.  Really has no practical value I can see though for a FPGA device user.  Why would you care how many LUT inputs you use?

l.e.o.

 

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Explorer
Explorer
1,341 Views
Registered: ‎06-25-2014

Interesting question...

Maybe the command is being ignored because the device you are using has no LUT4's. I believe this command is not telling the tool to map only up to 4 inputs to a lut, it is saying only use the LUT4 primitives in the fabric. 

 

I also don't get why you would want to do this?

It's only going to lead to slower speed and inefficient mapping into fabric logic. Only thing I can think is this is some way for you to compare against ASIC cells?

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Visitor
Visitor
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Registered: ‎10-26-2019

The device I am using has 4 LUTs and 6 LUTs. I still haven't managed to set the max_lut_input flag. The reason why I want this is that it is an assignment.

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Teacher
Teacher
1,309 Views
Registered: ‎07-09-2009

What Xilxin device are you targeting for this

  I di dnot relaise there were any devices with 4 and 6 input LUTs,

      Older Xilinx devices have 4 input LUTs, there were some great research studies as to why 4 was an optimum size at the time, Silicon area V complexity.

back in the orriginal days when Xilinx invented the FPGA .

 

You can instantiate in code 1,2,4 or 6 input LUTs

  be that schematic or RTL,

      the lut sizes you instantiate are just for user conveniance,

     When it comes to synthesis / mapping the device only has one size LUT in it ,

           In essance, the tools fill in the missing inputs for you .

 

 

  

 

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Teacher
Teacher
1,305 Views
Registered: ‎07-09-2009

some background on the LUT question

https://www.xilinx.com/support/documentation/white_papers/wp284.pdf

 

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Visitor
Visitor
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Registered: ‎10-26-2019
xa7z010clg400-1I is the device. I guess it doesn't really matter what device it is but since this is the one that has been used in the script, it's the one I'm using. In any case, this still is beyond the point.
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Teacher
Teacher
1,299 Views
Registered: ‎07-09-2009

That device only has 6 input LUTs,

   you can use nothing else.

 

 

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Teacher
Teacher
1,282 Views
Registered: ‎07-09-2009

This is interesting

Been reading UG901

seems you can use max_lut_input to limit what size LUTS are infered

  Still dont know why one would , but that s not relavant, I'd just liek to learn,

Where are you looking to see the LUT sizes used ?

If you look in vivado synthesis report utilization, that shoudl show you, but rember in the silicon they are still 6 input LUTs.

e.g.

+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE     |  550 |            Register |
| INBUF    |  390 |                 I/O |
| IBUFCTRL |  390 |              Others |
| LUT2     |  322 |                 CLB |
| CARRY8   |   52 |                 CLB |
| LUT1     |   37 |                 CLB |
| OBUF     |   29 |                 I/O |
| LUT3     |   12 |                 CLB |
| DSP48E2  |   12 |          Arithmetic |
| LUT4     |   10 |                 CLB |
| LUT5     |    8 |                 CLB |
+----------+------+---------------------+

 

 

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1,163 Views
Registered: ‎01-22-2015

@apbianco 

     Ok, I tried doing that but I can't get it to work.

As shown on page 71 of UG901(v2019.1), the format of the command is:

set_property BLOCK_SYNTH.MAX_LUT_INPUT 4 [get_cells <instance_name>]

In your use of the command, you did not specify <instance_name>. 

When you supply the <instance_name> of a module/component in your design, then the command should prevent use of LUT5 and LUT6 in that instance of the module/component.

Mark

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Newbie
Newbie
1,081 Views
Registered: ‎10-31-2019

Im working with op @apbianco . We tried giving it the top level PortaoGaragem but it doenst work:

set_property BLOCK_SYNTH.MAX_LUT_INPUT 4 [get_cells PortaoGaragem]

We also tried feeding it the specific instance name but that didn't work either:

set_property BLOCK_SYNTH.MAX_LUT_INPUT 4 [get_cells FSM_sequential_estadoAtual[1]_i_1]

We are also not sure at which point we execute the command. It is not possible to run it before synthesis because the cells haven't been instantiated. What we have been doing is running synthesis then the commands above, then synthesis again. Would like to know if that is correct as that might be the part of the problem also.

This is our only vhdl file in the project.

 

library ieee;
use ieee.std_logic_1164.all;

entity PortaoGaragem is
	port(
		clock, reset: in std_logic;
		SA, SF, SO, CR: in std_logic;
		MT: out std_logic_vector(1 downto 0)
	);
end;

architecture FSM of PortaoGaragem is
	type TipoEstado is (Aberto, Abrindo, Fechado, Fechando);
	signal estadoAtual, proximoEstado: TipoEstado; 
begin
	-- elemento de memória
	process(clock, reset) is
	begin
		if reset='1' then
			estadoAtual <= Fechando;
		elsif rising_edge(clock) then
			estadoAtual <= proximoEstado;
		end if;
	end process;
	-- lógica de proximo estado
	process(estadoAtual,SA, SF, SO, CR) is
	begin
		proximoEstado <= Fechando;
		
		case estadoAtual is
			when Fechado =>
				if CR='1' then 
					proximoEstado <= Abrindo;
				else
					proximoEstado <= Fechado;
				end if;
			when Abrindo =>
				if SA='1' then
					proximoEstado <= Aberto;
				else
					proximoEstado <= Abrindo;
				end if;
			when Aberto =>
				if CR='1' then
					proximoEstado <= Fechando;
				else
					proximoEstado <= Aberto;
				end if;
			when Fechando =>
				if SO='1' then
					proximoEstado <= Abrindo;
				else
					if SF='1' then
						proximoEstado <= Fechado;
					else
						proximoEstado <= Fechando;
					end if;
				end if;
		end case;
	end process;
	-- lógica de saída
	with EstadoAtual select
		MT <= "00" when Aberto,
				"11" when Fechando,
				"01" when Fechado,
				"10" when Abrindo;
end;



 

 

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1,066 Views
Registered: ‎01-22-2015

@raspasc 

I’m not sure how it all works if PortaoGaragem is the top-level VHDL component (ie. the only component) in your design.

Try making another VHDL component for use as the top-level component.  In this new top-level component, you will simply declare and instantiate PortaoGaragem.

So, if you instantiate PortaoGaragem into the top-level component with code that looks like the following:

pginst: PortaoGaragem
port map(
     clock =>…..,
     reset =>….,
     ….
     MT => ….
     )

...then, in the Vivado .xdc constraints file, you should place the following Tcl command:

set_property BLOCK_SYNTH.MAX_LUT_INPUT 4 [get_cells pginst]
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Visitor
Visitor
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Registered: ‎10-26-2019

markg@prosensing.com wrote:

@raspasc 

I’m not sure how it all works if PortaoGaragem is the top-level VHDL component (ie. the only component) in your design.

Try making another VHDL component for use as the top-level component.  In this new top-level component, you will simply declare and instantiate PortaoGaragem.

So, if you instantiate PortaoGaragem into the top-level component with code that looks like the following:

pginst: PortaoGaragem
port map(
     clock =>…..,
     reset =>….,
     ….
     MT => ….
     )

...then, in the Vivado .xdc constraints file, you should place the following Tcl command:

set_property BLOCK_SYNTH.MAX_LUT_INPUT 4 [get_cells pginst]

I'm not sure how to go about what you've just said. So we tried doing it with another project that is hierarchical, but it didn't work.

PortaoGaragem is the top-level VHDL component and the only component in the project. 

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Xilinx Employee
Xilinx Employee
1,011 Views
Registered: ‎06-14-2018

Hi @apbianco ,

I tried your testcase and tool applied BLOCK SYNTH.MAX_LUT_INPUT property correctly.

This is already covered here in discussion, BLOCK_SYNTH properties are applied on hierarchical blocks and not on top level.

Attached is snapshot when MAX_LUT_INPUT property is applied with value as 4. Also attached testcase.

Thanks,

apetley

 

 

View solution in original post

BLOCK_SYNTH.JPG
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Xilinx Employee
Xilinx Employee
422 Views
Registered: ‎11-03-2016

It can be used in heavily congested design which make heavy use of LUT6. Limiting to LUT4 bloats the design and allows the tools to choose more tracks to route the design. This requires that you have both the spare LUTs and timing slack.
It's something I see useful with CRCs and FECs in today's wide bus and "slow" clock designs where bits interact with each other often using long wires (which only go 12 CLBs away and require going through a short wire in and out). With more LUTs, you end up needing less long wires, you spread your design a bit leading to less congestion and more tracks/pips to route the design. Counter-intuitively, you end up with better timing QoR.

Regards,

YL

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