cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Voyager
Voyager
252 Views
Registered: ‎04-12-2012

Limitations of Unpacked Arrays in Systemverilog

Jump to solution

Hello,

Systemverilog has 2 array types: "packed" and "unpacked". 

As far as I understand - unpacked arrays can accept types that packed arrays cannot.
So why not  make a rule and elusively use unpacked arrays in the design ?
What limitations do unpacked arrays have ?

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Scholar
Scholar
200 Views
Registered: ‎09-16-2009

Re: Limitations of Unpacked Arrays in Systemverilog

Jump to solution

SystemVerilog packed array are powerful tools.  In fact we do the opposite to your suggestion and almost exclusively use packed arrays instead of unpacked.

Packed arrays, (and structures, and unions) can be used with more operators than unpacked types.  They are Integral types according to the standard - thus many more operations can be done with them - see Table 11-1 "Operators and data types" from the 1800-2012 standard. i.e all arithmetic operators are valid on packed types. Not with unpacked.

Regards,

Mark

View solution in original post

3 Replies
Highlighted
Scholar
Scholar
201 Views
Registered: ‎09-16-2009

Re: Limitations of Unpacked Arrays in Systemverilog

Jump to solution

SystemVerilog packed array are powerful tools.  In fact we do the opposite to your suggestion and almost exclusively use packed arrays instead of unpacked.

Packed arrays, (and structures, and unions) can be used with more operators than unpacked types.  They are Integral types according to the standard - thus many more operations can be done with them - see Table 11-1 "Operators and data types" from the 1800-2012 standard. i.e all arithmetic operators are valid on packed types. Not with unpacked.

Regards,

Mark

View solution in original post

Highlighted
Voyager
Voyager
178 Views
Registered: ‎04-12-2012

Re: Limitations of Unpacked Arrays in Systemverilog

Jump to solution

1.Can you please provide a document to the link you're referring to ?
2.I come from VHDL background and most of my interest is in synthesizable Systemverilog - when would it be wiser to use unpacked arrays in synthesis ?

0 Kudos
Highlighted
Scholar
Scholar
172 Views
Registered: ‎09-16-2009

Re: Limitations of Unpacked Arrays in Systemverilog

Jump to solution

@shaikon wrote:

1.Can you please provide a document to the link you're referring to ?


I'm referring to the IEEE 1800 SystemVerilog Standard.  If you're an IEEE member, I believe you can download it for free.  Ask your favorite search engine.  Highly recommended for any person using SystemVerilog in any form.


@shaikon wrote:

2.I come from VHDL background and most of my interest is in synthesizable Systemverilog - when would it be wiser to use unpacked arrays in synthesis ?


Early on, synthesizer vendors suggested that unpacked arrays could be implemented more efficiently. I'm doubtful that this is the case - at least in general - for modern synthesis tools.  Like I said, our whole team almost exclusively uses (multi-dimensional) packed arrays - in synthesizable code.  Unpacked array is the exception not the rule for us.  A VHDL user may prefer unpacked arrays, because it's more strongly typed, similar to VHDL - emitting compile time errors when array dimensions don't exactly match.  But verilog users have always been fast and loose with assignment, relying on verilog's built-in extension, and truncation rules.  Whether or not you think that's a good thing is up to you.  For us, the ability to treat a packed array as an integral type outweighs any drawbacks.

Regards,

Mark