12-05-2018 01:04 PM
Here is the code which I would like to implement
type t_ramType is array (0 to 2**g_AddrWidth-1) of std_logic_vector(g_DataWidth-1 downto 0); shared variable ram : t_ramType := (others => (others => '0')); signal readB : std_logic_vector(8*g_DataWidth-1 downto 0); begin process (CLK_in) variable BVec : std_logic_vector(g_AddrWidth-1 downto 0); begin if rising_edge(CLK_in ) then if (Enab_in = '1') then BVec := Addr_in ; for ii in 0 to 7 loop BVec(2 downto 0) := std_logic_vector(to_unsigned(ii, 3)); readB((ii+1)*g_DataWidth-1 downto ii*g_DataWidth) <= ram(to_integer(unsigned(BVec))); end loop; ram(to_integer(unsigned(Addr_in ))) := Data_in ; end if; if (Force_in = '1') then Data_out <= (others => '0'); else Data_out <= readB; end if; end if; end process; end behavioral;
Here it can been seen that huge register set is assigned as matrix and the tool after synthesizing it convert it to block RAM. As the reading the memory location is done in a for loop , 8 location are read in one cycle.
My question is in zynq ultrascale +, how it get converted or can be implemented ? I would like to use UltraRAM and BlockRAM combination, how can I do that ?
12-22-2018 10:40 AM
12-22-2018 11:03 AM