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Visitor agknaton
Visitor
271 Views
Registered: ‎09-23-2019

Load data from verilog HEX file into 4 8-bit BRAM instances for synthesis

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Hello,

I'm trying to get the contents from 1 verilog HEX file into 4 different BRAM instances. The code below works perfectly in simulation but for synthesis I get the warning "[Synth 8-311] ignoring non-constant assignment in initial block [".../cmsdk_fpga_rom.v":110]" and the BRAM don't get initialized.

      $readmemh(filename, fileimage);
      // Copy from single array to splitted array
      for (i=0;i<AWT; i= i+1)
        begin
        BRAM0[i] = fileimage[ 4*i];
        BRAM1[i] = fileimage[(4*i)+1];
        BRAM2[i] = fileimage[(4*i)+2];
        BRAM3[i] = fileimage[(4*i)+3];
        end

As a workaround I've manually split the contents of the verilog HEX file into 4 different files and load it with the code below. It works but it's cumbersome to this manual split in the files everytime.

      $readmemh({filename, "0"}, BRAM0);
      $readmemh({filename, "1"}, BRAM1);
      $readmemh({filename, "2"}, BRAM2);
      $readmemh({filename, "3"}, BRAM3);

Any ideas on how to make the first code snippet work on synthesis?

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Xilinx Employee
Xilinx Employee
144 Views
Registered: ‎07-21-2014

Re: Load data from verilog HEX file into 4 8-bit BRAM instances for synthesis

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Hi @agknaton 

 

Loading data from a variable in initial block is not supported in synthesis. 

There are only two ways we can proceed from here-

1- Have separate INIT files for each RAM.

or

2- Declare a parameter in header file and define it with the required values. You can then use this parameter to initialize RAM.

 

-Shreyas  

 

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5 Replies
Xilinx Employee
Xilinx Employee
259 Views
Registered: ‎05-22-2018

Re: Load data from verilog HEX file into 4 8-bit BRAM instances for synthesis

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Hi @agknaton ,

Check the below post solution, i guess it will resolve your issue:

https://forums.xilinx.com/t5/Synthesis/Problem-with-readmemh-at-synthesis-in-Vivado/td-p/335507 

 

if you have $readmemh and later on you use <>[i] to get the ith row, where i is an integer or genvar, $readmemh will not be able to read the file. If you want to access "table" row by row you have to use a wire or a reg as the index.

Also check post from Gabor form this thread:

https://groups.google.com/forum/#!topic/comp.lang.verilog/dNpv57FU79A 

Thanks,

Raj

 

 

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Visitor agknaton
Visitor
228 Views
Registered: ‎09-23-2019

Re: Load data from verilog HEX file into 4 8-bit BRAM instances for synthesis

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Thank you for your reply, unfortunately changing the type of "i" from integer to wire or reg doesn't solve the issue. I still get the same warning in synthesis.

To explain further the issue, I'll give an example:

  1. data.hex file has AA 7F 03 D8 42 ...
  2. fileimage gets those values just fine using $readmemh
  3. In the for loop the BRAMn instances should get:  BRAM0[0] = 0XAA, BRAM1[0] = 0x7F, BRAM2[0] = 0x03, BRAM3[0] = 0xD8, BRAM0[1] = 0x42 and so on.

In simulation it works just fine with the code mentioned in the original post. For synthesis I had to use the mentioned workaround otherwise BRAM0..3 are not initialized.

My question remains: how to initialize the BRAM0..3 values from the same data.hex file?

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Visitor agknaton
Visitor
190 Views
Registered: ‎09-23-2019

Re: Load data from verilog HEX file into 4 8-bit BRAM instances for synthesis

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Attached there is a minimal working example of the issue, hopefully this will clarify the issue. The forum is refusing the upload of the data.hex file, so I'm dumping its contents below.

What to see:

  1. In simulation the BRAM instances get properly initialized with the contents of data.hex file in all the right positions
  2. In synthesis the tool gives the warning: "[Synth 8-311] ignoring non-constant assignment in initial block [".../bram_bank.v":50]". As consequence, the BRAM instances don't get initialized with data. This is the problem.

Kind regards,

Agknaton

Contents of data.hex:

@00000000
40 F2 04 03 C2 F2 00 03 4F F2 80 02 C0 F2 FA 22 
1A 60 70 47 40 F2 04 03 C2 F2 00 03 4F F2 80 02 
C0 F2 FA 22 1A 60 70 47 2D E9 F0 41 27 4C 25 68 
D5 F8 48 41 84 B0 07 46 00 2C 41 D0 66 68 1F 2E 
1C DD 23 48 10 B9 4F F0 FF 30 1F E0 4F F4 C8 70 
E6 D1 D4 F8 8C 31 43 EA 00 02 C4 F8 8C 21 DF E7 
05 F5 A6 74 C5 F8 48 41 B8 E7 00 BF B4 26 00 00 
00 00 00 00 08 B5 00 21 04 46 00 F0 89 F9 04 4B 
18 68 C1 6B 01 B1 88 47 20 46 02 F0 43 F9 00 BF 
B4 26 00 00 70 B5 11 4B 11 4C 18 1B 81 10 18 D0 
04 EB 81 04 4E 1E 35 46 54 F8 04 2D 06 F0 01 06 
90 47 75 B1 26 B1 54 F8 04 3D 98 47 01 3D 08 D0 
54 F8 04 0D 80 47 01 3D 54 F8 04 1D 88 47 01 3D 
F6 D1 BD E8 70 40 02 F0 25 B9 00 BF 58 08 00 20 
54 08 00 20 F8 B5 20 4F 20 4C 38 1B 87 10 17 D0 
7A 1E 23 68 01 25 02 F0 01 06 98 47 AF 42 0F D0 
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Xilinx Employee
Xilinx Employee
170 Views
Registered: ‎07-21-2014

Re: Load data from verilog HEX file into 4 8-bit BRAM instances for synthesis

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Hi @agknaton 

 

I could reproduce the issue with a simple design.

I will let you know if this initialization is possible during synthesis

 

- Shreyas

----------------------------------------------------------------------------------------------
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Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
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Xilinx Employee
Xilinx Employee
145 Views
Registered: ‎07-21-2014

Re: Load data from verilog HEX file into 4 8-bit BRAM instances for synthesis

Jump to solution

Hi @agknaton 

 

Loading data from a variable in initial block is not supported in synthesis. 

There are only two ways we can proceed from here-

1- Have separate INIT files for each RAM.

or

2- Declare a parameter in header file and define it with the required values. You can then use this parameter to initialize RAM.

 

-Shreyas  

 

----------------------------------------------------------------------------------------------
Try to search answer for your issue in forums or xilinx user guides before you post a new thread.

Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
Give Kudos (star provided in right) to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
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