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sgilbertson
Observer
Observer
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Registered: ‎01-05-2012

Local library VHDL package constants don't work in out-of-context sources

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Is it supposed to be possible in Vivado 2016.4 to define constants in a VHDL package, in a source file contained in the project, and use those constants with the "library" and "use" statements in a VHDL source set for out-of-context synthesis?

 

If so, what am I missing?

 

To speed up synthesis when I'm making minor changes, I right-clicked some of my VHDL design sources and selected "Set as Out-of-Context for Synthesis...". Doing so disturbs passing of constants in a "generic" block, though, so I looked for a way to define some key constants globally, rather than passing them down through the hierarchy.

 

I updated some of the VHDL design sources to use a locally-defined library of constants, defined as a VHDL package, and to use the constants found in that library:

 

library my_lib;
use my_lib.my_constants.ALL;

entity some_entity is
Generic
( SOME_PARAM : integer := SOME_CONSTANT_DEFINED_IN_MY_CONSTANTS
; ...

 

In the "Libraries" tab, my_constants.vhdl appears under Design Sources / VHDL / my_lib. In its properties "Used-in" is checked for both Synthesis and Simulation.

 

I get "ERROR: [Synth 8-4169] error in use clause: package 'my_constants' not found in library 'my_lib', but only for design sources set to out-of-context.

 

If I right-click the offending design source and select "Unset Out-of-Context...", synthesis succeeds, without any changes to any of the VHDL sources. That's my workaround for now, but it results in long synthesis times.

 

 

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sgilbertson
Observer
Observer
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Registered: ‎01-05-2012

I have found the solution It's project-specific and my bad, to do with a generic constant being passed down from further up the hierarchy than I thought. I had forgotten to include the library from my top-level VHDL module.

 

I have a remaining issue with out-of-context synthesis, but it's one that's been reported elsewhere (such as this forum post), namely that Vivado doesn't let you nest out-of-context modules. Therefore when I have, say, a conditionally-generated ILA (which takes a long time to synthesize) under a large custom VHDL module (which also takes a long time to synthesize), I have to choose one or the other to be OOC. I guess it's not a bug, but I'm just registering my opinion that allowing nesting of OOC modules would be an improvement.

 

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anusheel
Moderator
Moderator
5,524 Views
Registered: ‎07-21-2014

@sgilbertson

 

I used an example code and it worked for me, check for DATA_WIDTH(constant declared in bftPackage) in below example:


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_SIGNED.all;

library bftLib;
use bftLib.bftPackage.all;

entity round_4 is
generic (
DATA_WIDTH : integer := 16
);
port (
clk : in std_logic;
x : in xType;
xOut : out xType
);
end entity round_4;

architecture aR4 of round_4 is
constant u : uType :=
(X"AF05",
X"50FA",
X"AE15",
X"51EA",
X"A2D5",
X"5D2A",
X"AC35",
X"53CA");

begin

transformLoop: for N in 0 to 7 generate
ct: entity bftLib.coreTransform(aCT)
generic map (DATA_WIDTH=> DATA_WIDTH)
port map (clk => clk, x =>x(N), xStep=>x(N+8), u=>u(N), xOut=>xOut(N), xOutStep =>xOut(N+8));
end generate transformLoop;

end architecture aR4;

 

Thanks,
Anusheel
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sgilbertson
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Registered: ‎01-05-2012

Thanks @anusheel for confirming that it ought to work.

 

Strange... I just tried to reproduce it in a small project, and couldn't. The OOC module had no trouble using the library module's constants, using "library work;" and "use work.my_constants.all;".

 

I don't know what the difference is with my bigger project. For now, I'll just live with longer re-builds, but at some point I'll have another stab at figuring it out.

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anusheel
Moderator
Moderator
5,499 Views
Registered: ‎07-21-2014

@sgilbertson

 

Sure, feel free to post here if you get the same issue again in the future. Please close this thread by marking appropriate post as accepted solution. 

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
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Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------

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sgilbertson
Observer
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Registered: ‎01-05-2012

I have found the solution It's project-specific and my bad, to do with a generic constant being passed down from further up the hierarchy than I thought. I had forgotten to include the library from my top-level VHDL module.

 

I have a remaining issue with out-of-context synthesis, but it's one that's been reported elsewhere (such as this forum post), namely that Vivado doesn't let you nest out-of-context modules. Therefore when I have, say, a conditionally-generated ILA (which takes a long time to synthesize) under a large custom VHDL module (which also takes a long time to synthesize), I have to choose one or the other to be OOC. I guess it's not a bug, but I'm just registering my opinion that allowing nesting of OOC modules would be an improvement.

 

View solution in original post

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