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volta
Visitor
Visitor
2,960 Views
Registered: ‎08-05-2016

Location constraints, strings and Verilog

Hi!

 

I’ve write a VHDL code using the location constraints and the generate statement and now I want to translate the same code to Verilog.

 

The VHDL code looks like this:

                attribute LOC of INV1:label is "X" & integer'image(i)& "Y" & integer'image(j);

 

Unfortunately when using Verilog, the concatenation operator { , } and the string data type don´t work the same as VHDL. For example

                This sentence works:                    (* LOC = "SLICE_X25Y63" *)

                This sentence doesn´t work:     (* LOC = {"SLICE_X25Y","63"} *)

 

In theory the string "SLICE_X25Y63" should be exactly the same as {"SLICE_X25Y","63"} but the LOC constraint can only work with the first one.

 

Is there any way to successfully translate my VHDL sentence to Verilog?

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allanherriman
Mentor
Mentor
2,921 Views
Registered: ‎01-08-2012

I recall having a similar discussion back in 2003.

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muzaffer
Teacher
Teacher
2,677 Views
Registered: ‎03-31-2012

@volta unfortunately Xilinx doesn't do constant manipulation properly with Verilog so this is not doable. They have closed a SR I opened with "won't fix". 

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