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Visitor
Visitor
2,432 Views
Registered: ‎11-01-2013

Logic Synthesis(bofore export IP) in Vivado_HLS

Hi,

 

I know that in Vivado HLS, before exporting IP, logic synthesis will automatically be performed by the appropriate Xilinx RTL synthesis product. What I'm confused is that, in UG902, it is said:

 

"

• 7-Series devices will use Vivado RTL Synthesis.
• Zynq and Non-7-Series devices will use ISE.

"

Isn't the programmable login in Zynq also 7-series FPGA. Why Zynq use ISE while 7-series use Vivao?

 

-Emily

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Xilinx Employee
Xilinx Employee
2,429 Views
Registered: ‎07-11-2011

Re: Logic Synthesis(bofore export IP) in Vivado_HLS

Hi,

 

This might be a  typo as I see below statement in the tool options and also at other sections like License required for RTL Export Flows in the doc.

 

"The default is option auto, in which case, Vivado will be used for Zynq and 7 series (and later) devices . ISE will be used for all other devices (6 series and earlier)."

 

 

Regards,

Vanitha.

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