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Visitor
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Registered: ‎03-22-2019

Logic function synthesis - target & source width mismatch

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I'm implementing a single logic function (with-select-when statement) in a VHDL file with 19 bits input and 10 bits output. The file has ~164K lines (cases). When I try to synthesize the file, Vivado reports an error saying that the output's target is 10 bits and the source is 11 bits. If I change the output's length to 9 bits (which is wrong, because it is actually 10 bits), Vivado reports that the target is 9 bits and the source is 10 bits (which is a correct error message).

If I try a similar file, which has 6 bits output, it synthesizes fine! Any idea as to what is happening? I've tried this with 2019 and 2020 version and I recreated the project in case that was the problem, but still the same error.

 

PS: I'm having problems posting code. For some reason whenever I post code, the post gets rejected and disappears from the board...

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Teacher
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Registered: ‎07-09-2009
ouch.

I would suggest , from experience, that some where in that file , you have a typing error ..

You are creating a PROM ?

The way to do that would be to make a coe file, and then use the Block Memory Generator

alternatively , you can code the contents as per UG901, page 158,

alternatively, and the way I tend to do for big files, is to use an external file to initialise an array.

https://vhdlwhiz.com/initialize-ram-from-file/



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Visitor
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Registered: ‎03-22-2019

 

The files are of the form:

entity test is
	Generic (
 		A : natural := 3;
		B : natural := 16;
		C : natural := 5;
		D : natural := 2 
 	        );
	Port ( address : in  STD_LOGIC_VECTOR (A+B-1 downto 0);
		output : out  STD_LOGIC_VECTOR (C*D-1 downto 0));
end test;


architecture Behavioral of test is

begin

with address select output <= 
	"0100110000" when "0000000000000000001",
	"0101111001" when "0000000000000000010",
                        .
                        .
                        .
	"1111000010" when "1001111111111111111",
	"----------" when others;

end Behavioral;

 

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Teacher
Teacher
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Registered: ‎07-09-2009
ouch.

I would suggest , from experience, that some where in that file , you have a typing error ..

You are creating a PROM ?

The way to do that would be to make a coe file, and then use the Block Memory Generator

alternatively , you can code the contents as per UG901, page 158,

alternatively, and the way I tend to do for big files, is to use an external file to initialise an array.

https://vhdlwhiz.com/initialize-ram-from-file/



<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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Visitor
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Registered: ‎03-22-2019

@drjohnsmith The file is (obviously) automatically generated from a script. That script generates both files (output width 6 & output width 10). Since the former synthesizes just fine, I do not think there is a typing error in the latter.

Also, I am mapping a logic function. I do not want - for now - to map into BRAMs, because I want to know the LUTs required for each function.

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Teacher
Teacher
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Registered: ‎07-09-2009
In sorry, it was not obvious to myself that the code had been generated by other code,
when others have reported similar on the forum in the past, and had similar errors reported, then typing / format was a common problem, hence my first suggestion.

That the file is generated is good,
a few things,

You have 164000 lines plus of code ?
the tools are going to expand all the logic options out, and then try to simplify, with that others "--- --" at the end, that's going to be VERY big lump of code,

I'm really not certain the tools have been pushed that far, its just not how code is normally codded.

Just a quick note on the file format, to make it easier to read,
Try coding the "0100110000" as B"01_0011_0000"

I'd also try the case format instead of the when format,
the tools are in my experience better at coping with large case statements, but again its still a large set.

Can I ask why you do not want to put the output into a Ram ? Id be surprised if the system does not put it into RAM,

As a final suggestion,
you seem to be implying that each of the output bits is a function,

I'm just wondering, is one of the "functions" get reduced out.

Try making a table with all the inputs , and just one bit out.
For 10 bits out, you make 10 tables,
OK, it would be massive, but as you say, its generated code, so no typing needed.

What you will then have in the above case, is 10, single out and 16 bits in gate. Your logic reduced function,





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Visitor
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Registered: ‎03-22-2019

You were indeed right! The error was caused by a single case, where the output was 11 bits and not 10. This was due to an overflow in the generator script. Despite me explicitly requesting n bits, the python function returned the maximum number of bits between n and the minimum length of the word. I had to scroll through every line in the file to detect the anomaly (wish Vivado would report the specific line as well).

Just a quick note on the file format, to make it easier to read,
Try coding the "0100110000" as B"01_0011_0000"

Thanks, that is a very nice trick! I didn't know that...

 

Can I ask why you do not want to put the output into a Ram ? Id be surprised if the system does not put it into RAM,

I am running some experiments and I want to measure who many LUTs these logic functions will take up. Whether, in the final design, these functions will be mapped onto BRAM or logic will depend on what resources the rest of the design will require. As a side note, if you need high throughput from these functions, you may be bound to use logic.

 

Thanks again for the help and the very interesting suggestions @drjohnsmith !