01-05-2020 11:47 PM
I am trying to migrate design from Vivado 2018.2 version to 2019.2 version. I have upgraded all Xilinx IP's in the design instead of re-configuring and regenerating it.
In the synthesis netlist, I see that 90% of the logic is getting trimmed in comparison to the 2018.2 version.
The only change in design is the up-gradation of IP's.
What could be the possible cause of this?
01-06-2020 12:03 AM
How did you know 90% logic was getting trimmed? By looking at the Synthesis utilization report?
Where did you check the Utilization report?
This AR may be helpful for your question:
01-06-2020 01:05 AM
And compared with the same part in synthesis runme.log of 2018.3?
01-06-2020 05:42 PM
Can you provide the two Synthesis log files?