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Anonymous
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MIG IP OOC Synthesis never ends

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Hello Everyone,

 

I have problem with MIG IP ooc sysnthesis process. Here is what I've chronologically experienced about the problem;

 

I have

Step1: integrated the MIG IP into my design.

Step2: synthesized the IP (in ooc mode) and the design code.

Step3: loaded the bit file to target and observed the phy has active (means phy_init_done is Logic-1)

Step4: integrated ILA to see the internal signals (SDR user interface IP control signals)

Step5: synthesized again and changed the ILA signals (I've added the address and data signals)

Step6: synthesized again

Step7: observed that ILA dashboard has not opened.

Step8: reset the synthesis by right clicking to "Run Synthesis" button.

Step9: (same condition Step7)

Step10: Step8 + reset  all ooc module synthesis

Step11: started the ooc sysnthesis again (without overall design synthesis)

Step12: got the follwing error:

HATA2.png

Step13: put the following tcl command to overcome the problem and it worked;

             set_param synth.elaboration.rodinMoreOptions {set rt::extractNetlistGenomes false} 

Step14: run the synthesis again. And, synthesis never ends right now (by the way, I've checked the license, and there is no problem with it).

MIG_Synt.png

 

I've thought that something gone wrong in the project setting or somewhere. And I created a new project.

I've only added the MIG IP into the new project and started the synthesis. Problems goes on..

 

Any suggestion for this problematic situation?

 

Thanks in Advance,

Batu

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Moderator
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4,806 Views
Registered: ‎07-21-2014

Re: MIG IP OOC Synthesis never ends

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@Anonymous

 

Not sure on why IP synthesis didn't work in 2016.2 for your machine. Good to hear that with 2016.4 you are able to complete OOC synthesis. Please close this thread by marking appropriate answer as "Accept as solution" .

 

Thanks,
Anusheel
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Moderator
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Registered: ‎07-21-2014

Re: MIG IP OOC Synthesis never ends

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@Anonymous

 

Did you test this flow in 2016.4 instead of 2016.2? Also, share the OS information.

set_param synth.elaboration.rodinMoreOptions {set rt::extractNetlistGenomes false} -- Did you get this param from Xilinx?

 

Thanks,

Anusheel

 

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Anonymous
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Re: MIG IP OOC Synthesis never ends

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@anusheel

OS of my computer is 64bit win7-enterprise edition. Our IT department has rebuilt my computer. And now I'm using 2016.4 version without any problem.

I have no idea what was wrong on my computer.

 

Best Regards,

Batu

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Highlighted
Moderator
Moderator
4,807 Views
Registered: ‎07-21-2014

Re: MIG IP OOC Synthesis never ends

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@Anonymous

 

Not sure on why IP synthesis didn't work in 2016.2 for your machine. Good to hear that with 2016.4 you are able to complete OOC synthesis. Please close this thread by marking appropriate answer as "Accept as solution" .

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------

View solution in original post

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