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sapan533
Observer
Observer
9,274 Views
Registered: ‎06-10-2015

Mapping signal names before and after synthesis

Hi,

 

I want to know if there is any way by which we can have the mapping between signal names before and after synthesis?

 

I want to have the mapping between RTL signals which is input to Vivado Synthesis and the signals in synthesized netlist.

 

Rgds

Sapan

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6 Replies
nupurs
Moderator
Moderator
9,271 Views
Registered: ‎06-24-2015

Hi,

Apply DONT_TOUCH property. Refer to this link for details:
http://www.xilinx.com/support/answers/57727.html

 

Usage of DONT_TOUCH is as follows:

 

Verilog Example
(* dont_touch = "true" *) <signal_name>;

 

VHDL Example
attribute dont_touch : string;
attribute dont_touch of <signal_name> : signal is "true";


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Thanks,
Nupur
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arpansur
Moderator
Moderator
9,265 Views
Registered: ‎07-01-2015

Hi @sapan533,

 

You can make use of hierarchical filter and * to use in XDC before synthesis.

For e.g; 

[get_cells -hierarchical -filter { NAME =~  "*ibufds_instQ0_CLK1*" } ]

can be replaced with 

[get_cells mgtEngine/gt_usrclk_source/ibufds_instQ0_CLK1]

 

You can also go through the following link
http://www.xilinx.com/support/answers/62136.html

 

Thanks,
Arpan

Thanks,
Arpan
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sapan533
Observer
Observer
9,248 Views
Registered: ‎06-10-2015

@nupurs

This wont be a perfect solution as it will require me to change RTL everywhere. I am looking to use this mapping during readback. And i want to map the signal names in logic location file to that in the RTL.

 

 

RGds

Sapan

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dwisehart
Scholar
Scholar
9,242 Views
Registered: ‎06-23-2013

If you set -flatten_hierarchy in the Synthesis settings to 'none' you will be a lot better off because the names won't change. I usually find that I get better timing with it set to none as well.

Daniel
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sapan533
Observer
Observer
9,229 Views
Registered: ‎06-10-2015

@dwisehart

 

Hi Daniel,

 

Thanks for the answer. That sounds a better option than others. But if we do not set flatten_hierarchy to NOne, is it still possible to have the signal names mapping from Vivado? I am sure there must be some way to get this information.

 

RGds

Sapan

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dwisehart
Scholar
Scholar
9,220 Views
Registered: ‎06-23-2013

Not that I am aware of, Sapan, and I have looked for this type of functionality.

 

Daniel

 

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