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6,941 Views
Registered: ‎07-24-2018

Meaning of synthesis warning: [Constraints 18-5210] No constraint will be written out.

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Hi all,

 

I get this warning (since vivado 2018.2):

[Constraints 18-5210] No constraint will be written out.

 

What does it mean? I guess it can be ignored as I don't see any issue and I have my usual constraints set (physical, timing, ...) which should not require any changes in/after synthesis. So, I'm not sure what to do with this warning other than suppressing.

 

 

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wfjmueller
Explorer
Explorer
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Registered: ‎11-23-2009

Hi @hemangd,

 

I also see this warning. It came with 2018.2, I don't see it with 2018.1, 2017.4 and 2017.2.

It comes at the very end of synthesis

synth_design completed successfully
synth_design: Time (s): cpu = 00:02:50 ; elapsed = 00:03:41 . ...
WARNING: [Constraints 18-5210] No constraint will be written out.
INFO: [Common 17-1381] The checkpoint '....dcp' has been generated.

So this message does not refer to a cell. it refers to the whole design.

And 'no constraint written' sounds at first scary.

Further inspection of my case showed that implementation seems properly constrained, so it seems to be true that this message can be safely ignored.

 

This message text should imho at least be rephrased, to be more specific, giving a chance to understand what is behind, to indicate the case where this message better not be ignored. It is imho sub-optimal to write out scary sounding warnings which should generally be ignored.

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hemangd
Moderator
Moderator
6,922 Views
Registered: ‎03-16-2017

Hi daniel.widmer@varian.com,

 

This WARNING message is expected when there is no constraints in top-level related to those cells.

 

You can safely ignore it. 

 

Regards,

hemangd

 

If your issue has been resolved, than please close this thread by marking as accepted solution.

 

Regards,
hemangd

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wfjmueller
Explorer
Explorer
7,019 Views
Registered: ‎11-23-2009

Hi @hemangd,

 

I also see this warning. It came with 2018.2, I don't see it with 2018.1, 2017.4 and 2017.2.

It comes at the very end of synthesis

synth_design completed successfully
synth_design: Time (s): cpu = 00:02:50 ; elapsed = 00:03:41 . ...
WARNING: [Constraints 18-5210] No constraint will be written out.
INFO: [Common 17-1381] The checkpoint '....dcp' has been generated.

So this message does not refer to a cell. it refers to the whole design.

And 'no constraint written' sounds at first scary.

Further inspection of my case showed that implementation seems properly constrained, so it seems to be true that this message can be safely ignored.

 

This message text should imho at least be rephrased, to be more specific, giving a chance to understand what is behind, to indicate the case where this message better not be ignored. It is imho sub-optimal to write out scary sounding warnings which should generally be ignored.

View solution in original post

hemangd
Moderator
Moderator
6,844 Views
Registered: ‎03-16-2017

Hi @wfjmueller,

 

Can you share a small test case which consists of a source file and constraints file (.xdc) to debug this warning in detail?

 

If this warning and its message is not relevant/need a rephrase than we may discuss this issue with the factory on it and may ask for necessary changes in the tool. 

 

Regards,

hemangd 

Regards,
hemangd

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patneva
Observer
Observer
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Registered: ‎07-30-2018

I am also getting the same error - but what is meaning of ignoring it? coz it doesnt generate bit file so cant run the program on hardware

I am doing simple program of led blinking from you tube. I am using zedboard as reference hardware

bitstream error.jpg
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wfjmueller
Explorer
Explorer
6,689 Views
Registered: ‎11-23-2009

Hi @hemangd

 

please find attached a Vivado 2018.2 project which shows the [Constraints 18-5210] message.

The project definitively has constraints, starting with pin assignments.

 

With best regards,   Walter

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hongh
Moderator
Moderator
6,673 Views
Registered: ‎11-04-2010

Hi @patneva ,

Please create a new thread for your Design Initialization Error. 

Warning [Constraints 18-5210] is not the cause for your error you met.

 

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hongh
Moderator
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Registered: ‎11-04-2010

Hi, @wfjmueller ,

The warning can be seen in the example design in Vivado.

Actually Warning [Constraints 18-5210] reminders you that the synth.dcp generated in ./project_name.runs/synth_1/ dir doesn't contain any constraint. 

When you generate the synth.dcp with the below method, the warning disappears and no constraints are missing:

<1>. Open synthesized design

<2>. write_checkpoint synth.dcp

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m3atwad
Voyager
Voyager
5,006 Views
Registered: ‎05-25-2016

@hongh I have this exact same problem.  I don't understand your answer regarding why constraint error 18-5210 is generated.  

 

Why wouldn't the dcp contain a constraint if there is a constraint correctly added to the project?  I've run synthesis and implementation on this and I can't get rid of this warning?  I am also creating this project from a script usually so I don't save the dcp or anyof that project related data.  What is the appropriate manner for satisfying this warning?  

Questions

1. Why doesn't the dcp have a constriant when the dcp is created with a project that has a top level constriant?

2. How do you correctly satisfy this warning when building your project from a TCL script?  

2.a. How do you tell vivado to build a TCL script that will prevent this warning from appearing?  I'm using "write_project_tcl" right now.

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marcb
Moderator
Moderator
2,711 Views
Registered: ‎05-08-2012

I wanted to update this thread, since there have been additional posts.

This message will be removed for the 2020.1 release of Vivado, as it has caused much confusion.

 

For designs that have synthesis constraints applied, part of the message indicates that how project mode constraints are handled in Vivado. Below is from the message.

This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.

 

Project mode constraints are read in during synthesis, used, but not written to the <project_name>.runs/synth_1/<project_name>.dcp file. Instead constraints are read in again at the beginning of implementation, or when opening the synthesized design. This highlights the difference between "open_checkpoint <project_name>.runs/synth_1/<project_name>.dcp" and selecting "Open Synthesized Design".   

 

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Agner
Visitor
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Registered: ‎05-08-2020

Sorry, I don't get it. Where do I put "write_checkpoint synth.dcp" ?

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