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Voyager
Voyager
419 Views
Registered: ‎04-11-2016

Measure clock inside rtl

Hi,

I have a refence clock of 100 MHZ. I would like to measure another clock which is varying in frequency.

I would like to know Is there any way to measure other clock with a reference clock(100 MHz in my case) inside RTL(system verilog) lets say by means of scanning the pulse and counter?

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6 Replies
Scholar
Scholar
411 Views
Registered: ‎08-07-2014

@fpgalearner,

Can be done, but I think your clk to be measured will have a frequency restriction wrt the ref clk (100M).

 

https://forums.xilinx.com/t5/Virtex-Family-FPGAs-Archived/Clock-frequency-calculation-measurement-using-Virtex-FPGA/td-p/659251

https://iopscience.iop.org/article/10.1088/1748-0221/15/03/P03012/pdf

 

 

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Xilinx Employee
Xilinx Employee
400 Views
Registered: ‎01-30-2019

HI @fpgalearner 

haven't tried my self but just a rough Idea: 

Run two counters, one using A 100 Mhz and another B using the unknown freq. 
Generate a Control circuitry such that it will be applied to both the counters and it will run A counter for only 1-2 or some finite number of counts.
Read the count values of both counters, you will get a relation like X cycles of A = Y cycles of B thus Y/X is the relation between unknown freq and known

This will only work when unknown freq > known freq.

Hope this helps

Scholar
Scholar
392 Views
Registered: ‎08-01-2012

@surajc 

Surely if you run it for a known number of clocks in Domain A (the longer the better) then it doesnt matter if A is faster or slower than B, the ratio can be calculated. Obviously there may be a little jitter and synchronising the reset will be an issue, but the longer you run the sample the better.

Xilinx Employee
Xilinx Employee
388 Views
Registered: ‎01-30-2019

Hi @richardhead 
yes, you are correct, I think my thought process ( while writing the reply ) did not consider the other possibility. 

@fpgalearner Correction This will only work when unknown freq > known freq. As Richard said it will work, the tricky part is the reset ( control circuitry ) and in the other case ( unknown freq < known freq ) X/Y will be the relation.

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Scholar
Scholar
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Registered: ‎05-21-2015

@fpgalearner,

Yes, it can be done.  I've done it often.  The trick is to use a counter to slow the variable clock down so that it's within the range of the 100MHz clock, and then to count the slower transitions on the 100MHz clock.

See here for a discussion and an example design that has done nicely for me.  Resolution is 16Hz--far better than your hardware clocks will give you.

Dan

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Voyager
Voyager
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Registered: ‎04-11-2016

 
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