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Observer
Observer
688 Views
Registered: ‎12-21-2015

Memories not in synthesised design

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Hello,

 

I am using VIVADO 2018.3 and Ihave generated RAM blobk using xilinx memoiry generator. In RTl the RAms are properly instantiated, but synthesis report says no RAMs used


2. Memory
---------

+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 445 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 445 | 0.00 |
| RAMB18 | 0 | 0 | 890 | 0.00 |
+----------------+------+-------+-----------+-------+

 

I found this problem when I tried to access the memories in Genesys board.

The lowest level in synthesised schematic looks ( see attached picture). is the name of the block correct? DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram

Regards, skor

Capture.PNG
Capture.PNG
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Moderator
Moderator
622 Views
Registered: ‎07-21-2014

@skor 

Tool option "Open Synthesized Design" will load the .dcp file of IPs and hence you will see correct utilization. 
When you run synthesis of top module which has IPs marked as OOC then the run report will not include the utilization of IPs. 

Thanks
Anusheel 

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4 Replies
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Moderator
Moderator
686 Views
Registered: ‎07-21-2014

@skor 

Looks like the BRAM IP was synthesized as OOC. Can you open the synthesized design in Vivado and run utilization report(report_utilization)?

Thanks
Anusheel 

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Observer
Observer
676 Views
Registered: ‎12-21-2015

Hello,

I run report_utilisation. here is snapshot.

Capture1.PNG
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Xilinx Employee
Xilinx Employee
628 Views
Registered: ‎07-16-2008

Please refer to the below answer.

https://www.xilinx.com/support/answers/59282.html

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Moderator
Moderator
623 Views
Registered: ‎07-21-2014

@skor 

Tool option "Open Synthesized Design" will load the .dcp file of IPs and hence you will see correct utilization. 
When you run synthesis of top module which has IPs marked as OOC then the run report will not include the utilization of IPs. 

Thanks
Anusheel 

View solution in original post