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Observer nixiebunny
Observer
587 Views
Registered: ‎01-26-2009

Missing signal error for signal that is no longer in project source files

Hi, I am working on a large, mostly VHDL design using Vivado 2015.4. I have replaced a module supplied by my colleague with an earlier version of said module. I used the "remove source file from project" and "add sources" commands in the GUI to do this replacement.

 

I get this error when atetempting synthesis:

[Synth 8-3493] module 'demux' declared at '/home/arows/dualb/HDK/VPX6_474_UFPGA/eau/arowsdec-0.1.1/src/demux.vhd:27' does not have matching formal port for component port 'denab' ["/home/arows/dualb/HDK/VPX6_474_UFPGA/eau/arowsdec-0.1.1/src/decimate.vhd":139]

 

The signal 'denab' existed in the previous version of the decimate module, but it exists nowhere in the source tree of the project as it sits.

 

It's as if some phantom copy of the previous version of the module is being referenced internally by the synthesis tool. I have closed the project and reopened it, and I have reset_project.

 

How can I fix this problem?

 

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Observer nixiebunny
Observer
555 Views
Registered: ‎01-26-2009

Re: Missing signal error for signal that is no longer in project source files

I seem to have found the solution in the project file, a25g.xpr.

 

I opened this big XML file with my text editor, and found some instances of files from the previous module path. I updated the path to the current module path, and now the synthesis runs.

 

The files in question were referenced in a VHDL 'use' statement, so they didn't appear in the hierarchy, so I never had an opportunity to delete them from the hierarchy using the GUI.

 

So when the project drives you nuts, go ahead and edit the project's .xpr file. It will restore your sanity!

 

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