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Multi File Compilation Unit (mfcu) option to set different set of defines

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Visitor
Posts: 9
Registered: ‎03-19-2015

Multi File Compilation Unit (mfcu) option to set different set of defines

Hi,

 

I'm looking for mfcu option to set different defines for particular file independently. For example:

 

 

read_verilog {define1.vh mod1.v}

read_verilog {define2.vh mod2.v}

read_verilog {define3.vh top.v}

 

 

does NOT work. I need to use set of defines from define1.vh for mod.v file and so on.

 

In modelsim we have got -mfcu option:

vlog -mfcu define1.vh mod1.v
vlog -mfcu define2.vh mod2.v
vlog -mfcu define3.vh top.v

 

In Synplify this option is default:

add_file -verilog define1.vh mod1.v
add_file -verilog define2.vh mod2.v
add_file -verilog define3.vh top.v

only need to undef unnecessary `define by `undef pragma in next .vh file. Other EDA tools has often default support for mfcu, but Vivado seems does not have this kind of support. Maybe I'm missing something? Is there any way to handle this problem without changing .v files? Existence of -sfcu option suggests that -mfcu option is default option in Vivado - but it is NOT.

John.

Moderator
Posts: 1,467
Registered: ‎07-21-2014

Re: Multi File Compilation Unit (mfcu) option to set different set of defines

@pudzilla

 

Vivado uses multi-file CU by default. Can you please share a test case which is failing at your end? Also, try to test the design in latest version of Vivado if not done yet.

 

Thanks

Anusheel

Visitor
Posts: 9
Registered: ‎03-19-2015

Re: Multi File Compilation Unit (mfcu) option to set different set of defines

@anusheel

 

Testcase is attached. For mod1 I want to use define from define1.vh, for mod2 - define from define2.vh and so on.

 

John.

Xilinx Employee
Posts: 328
Registered: ‎03-16-2017

Re: Multi File Compilation Unit (mfcu) option to set different set of defines

[ Edited ]

Hi @pudzilla,

 

Edit as  `include "define1.vh" in top of mod1.v file and `include "define2.vh" in top of mod2.v and check the functional simulation.

Both or and xor logic of mod1 and mod2 is working and its shown in the comb_out1 output in functional simulation. 

 

Regards,

hemangd