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Contributor
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Registered: ‎01-06-2016

Multi-driven nets using verilog tasks

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Hi,

 

I'm getting a warning about multi-driven nets when a net is driven with a Verilog task in a large design. (It works in a smaller project.) It looks to me like the source is a signal replicated by synthesis. There is only a single target reg under a single clock domain. If I take out the task by replicating the task contents everywhere then I don't get the error. Am I misunderstanding something about tasks ?

It's almost useless to look at the elaborated schematic (22,000) nets. But it doesn't look like there are multiple drivers.

 

reg [5:0] state;

always @(posedge clk)

case(state)

... some state: next_state(STATE2);

... some state: next_state(STATE500);

... some state: next_state(STATE257);

endcase

 

// I have the following task to assign states.

task next_state;

input [5:0] st;

begin

      state <= st;

end

endtask

 

It's supposed to infer a multiplexer into the state register. It looks like it' can't do it when it replicates logic.

 

  • [Synth 8-3352] multi-driven net u1/u1/state[1] with 1st driver pin 'u1/u1/state_reg[1]/Q' ["C:/Cores4/DSD/DSD9/trunk/rtl/verilog/DSD9a.v":675]
  • [Synth 8-3352] multi-driven net u1/u1/state[1] with 2nd driver pin 'u1/u1/state_reg[1]__0/Q' ["C:/Cores4/DSD/DSD9/trunk/rtl/verilog/DSD9a.v":2070]
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Contributor
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Registered: ‎01-06-2016

Re: Multi-driven nets using verilog tasks

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Um, I was going to do that but I don't see a way as to how. There doesn't seem to be any menu selection or icon on-screen that would allow me to.

 

 

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Guide
Guide
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Registered: ‎01-23-2009

Re: Multi-driven nets using verilog tasks

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There doesn't appear to be anything inherently wrong with using tasks to assign the next state (although I wonder why you want to do so instead of simply saying "state <= STATE500")...

 

But the two drivers are separated by almost 1400 lines of code - are all 1400 lines of code part of this one state machine? The state variable is only 6 bits so it can't have more than 64 states (at first I worried that STATE500 was really the 500th state!) - so what is in those 1400 lines of code? Are you sure that these two lines of code are really in the same process?

 

Avrum

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Registered: ‎01-06-2016

Re: Multi-driven nets using verilog tasks

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There is about 800 lines of code in the state machine. There are a number of other tasks between the end of the state machine and the next_state() task. next_state() task is used because then a $display() can be put in it to show the state transitions and other information while debugging. The same problem crops up with several other tasks not just the next_state() task. Tasks are being used like macros/subroutines to avoid having the same code repeated over and over again in the text.

There are actually only about 50 different states which is why the state reg is only six bits. But the state is being set from dozens of places.

This problem was "fixed" with another design by removing all the tasks and replicating the text. But it's quite a challenge to update because of all the text changes required.

The design seems to run okay in simulation.

 

I'm wondering if anybody else has run into this problem ? The free web-pack version of Vivado is in use.

 

 

 

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Registered: ‎01-06-2016

Re: Multi-driven nets using verilog tasks

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I found the problem by manually expanding out the tasks. There was a task being used in another always block that depended on a task which would work only under the clock domain. The multi-driven nets message is gone now during synthesis.

 

 

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Moderator
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Registered: ‎06-24-2015

Re: Multi-driven nets using verilog tasks

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@rtfinch,

 

Glad to know that your issue is resolved. Please close this thread by marking your reply as "Accept as Solution" in the interest of other users.

Thanks,
Nupur
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Registered: ‎01-06-2016

Re: Multi-driven nets using verilog tasks

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Um, I was going to do that but I don't see a way as to how. There doesn't seem to be any menu selection or icon on-screen that would allow me to.

 

 

View solution in original post

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