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techway
Observer
Observer
8,888 Views
Registered: ‎02-17-2012

Multiple Assignment codign rule

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Hi all,

 

I have a very simple question concerning what is allowed or not in a VHDL process.

 

Up to, is it allowed to write this (for synthesis)?

 

my_proc: process(CLK)
    begin
      if rising_edge(CLK) then
          foo <= '0'      
          if bar='1' then
            foo <= '1';
          end if;
      end if;
    end process;

 

Same Question with :

my_proc: process(CLK)
    begin
      if rising_edge(CLK) then

          if bar_0='1' then
            foo <= '1';
          end if;

          if bar_1='1' then
            foo <= '0';
          end if;

      end if;
    end process;

Tx

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Accepted Solutions
anusheel
Moderator
Moderator
16,940 Views
Registered: ‎07-21-2014

@techway

 

if rising_edge(CLK) then
          foo <= '0'      
          if bar='1' then
            foo <= '1';
          end if;

Above statement is as good as bar directly connected to 'D'  pin of flop.

  if rising_edge(CLK) then

          if bar_0='1' then
            foo <= '1';
          end if;

          if bar_1='1' then
            foo <= '0';
          end if;

Suppose bar_0 and bar_1 both are '1' then the assignment after bar_1 condition will be updated (foo <= '0').

 

Thanks,
Anusheel
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View solution in original post

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5 Replies
anusheel
Moderator
Moderator
8,886 Views
Registered: ‎07-21-2014

@techway

 

Yes, you can use multiple if statements. 


   if <condition> then -- RST = '1'
      <statement>
    end if; 
      

Thanks,
Anusheel
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techway
Observer
Observer
8,874 Views
Registered: ‎02-17-2012

In fact the question was focused on the fact that foo is concurrently assigned with different values in the same process depending on which condition is true.

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anusheel
Moderator
Moderator
16,941 Views
Registered: ‎07-21-2014

@techway

 

if rising_edge(CLK) then
          foo <= '0'      
          if bar='1' then
            foo <= '1';
          end if;

Above statement is as good as bar directly connected to 'D'  pin of flop.

  if rising_edge(CLK) then

          if bar_0='1' then
            foo <= '1';
          end if;

          if bar_1='1' then
            foo <= '0';
          end if;

Suppose bar_0 and bar_1 both are '1' then the assignment after bar_1 condition will be updated (foo <= '0').

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------

 

 

 

 

View solution in original post

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evanslatyer
Explorer
Explorer
8,835 Views
Registered: ‎07-13-2015

The synthesis tool can handle multiple assignment within one block of code, in VHDL or Verilog. This is because within one block it has a simple rule to follow: the last assignment always wins. Following this rule ensures that the final value is unambiguous.

 

 

The problems occur when you assign values to one variable from different blocks. There is no rule that says which block gets executed first; in hardware they're  simultaneous, and the simulator uses whatever order it feels like. As a result, the synthesis tool cannot determine who gets to write.

 

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techway
Observer
Observer
8,819 Views
Registered: ‎02-17-2012

thank you for your detailed answer@evanslatyer

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