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Visitor
Visitor
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Registered: ‎06-12-2019

Multiple architecture let Synthesizer choose faster design?

I have an entity that can be designed with two different architectures. The entity is going to be instantiated multiple times in the whole design. Is there a way to let Vivado's synthesizer decide what architecture to use each time such that the area/timing is minimized? The reason I need this is because my second design consumes less area but would be worse at some point because of routing delay which is when the first architecture would be used.

I looked at configurations in VHDL but it seems that I have to decide which architecture to choose (from what I understood). Is the above possible in VHDL or SystemVerilog?

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Teacher
Teacher
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Registered: ‎07-09-2009

not really how the tools work,
they run till they meet the constraints you set and then stop.

also remember that the tools are going to rip the actual design apart, Especially so in systemV as its a higher level language.

So what you get is going to be a long way split from what you think .
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