Multiple architecture let Synthesizer choose faster design?
I have an entity that can be designed with two different architectures. The entity is going to be instantiated multiple times in the whole design. Is there a way to let Vivado's synthesizer decide what architecture to use each time such that the area/timing is minimized? The reason I need this is because my second design consumes less area but would be worse at some point because of routing delay which is when the first architecture would be used.
I looked at configurations in VHDL but it seems that I have to decide which architecture to choose (from what I understood). Is the above possible in VHDL or SystemVerilog?