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Hello, I have a small issue with my VHDL programming. Right now, I need to create a way of multiplyinig a constant number 0.05 by a number that will vary throughout the funtionning of the program, that I have declared as a variable integer. I do not know which library I can use or if it is even possible. I have seen that there is a fixed point option but I do not know if it is going to be capable of handling this operation and I do not know how to use it. It would be of great help if someone could give me an answer.

sebs

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03-07-2018 02:48 PM

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richardhead

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03-08-2018 12:42 PM

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08-01-2012

Take a read of synthesis UG901, https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug901-vivado-synthesis.pdf, specifically the section on VHDL 2008. It explains first you need to add the fixed library to your project (provided in Vivado as a '93 compatible version)

you need to include the library in your code (assuming comptear is unsigned)

use ieee.fixed_pkg.all;

realnumber<=to_ufixed(0.05,8,4)*to_ufixed(compteur1,8,4); output<=unsigned( realnumber(7 downto 0) );

But why make everything unsigned when you could just stick with ufixed?

7 Replies

markcurry

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03-07-2018 05:30 PM

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Re: Multiplication of fixed point by an integer

Are you having trouble with doing this in VHDL or is this a general fixed point number question?

For the latter, I suggest reviewing fixed point notation, and what's really happening. A small hint - you're just really multiplying two integers together (with some scale information kept on the side).

My favorite reference is:

https://courses.cs.washington.edu/courses/cse467/08au/labs/l5/fp.pdf

Regards,

Mark

richardhead

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03-07-2018 11:23 PM

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Re: Multiplication of fixed point by an integer

Fixed point arithmatic is nothing more than integer arithmatic with an offset. It is perfectly possible in FPGAs as FPGA fabric is designed around integer arithmatic.

You can do it without any special libraries, but VHDL 2008 introduced the fixed_pkg.vhd that helps users with the representation of fixed point values in the code (previously you have to use vectors/unsigned and keep track of where the integer/fractional parts were).

For example

signal usf : ufixed(3 downto -4); --unsigned fixed 4 bits integer 4 bits fractional

signal sf : sfixed(7 downto -10); -- signed fixed 8 bits integer 10 bits fractional.

In the vhdl, the multiplication can be as simple as:

result <= to_ufixed(0.05, 4,4) * usf;

sebs

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03-08-2018 11:04 AM

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03-07-2018

Re: Multiplication of fixed point by an integer

Richardhead, that's what I am actually looking for, but when I have tried to implement it an error sign has appeared. Maybe it is not a library problema, but a "use" problem. I am really sorry this might be a very easy problem but I am getting started and I do not know how to solve it. This is my program, and my issues are over the lines 79 and 80. Thanks beforehand to any kind of help.

library IEEE; --These are the libraries that I have called use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; And these are the lines where I have problems: realnumber<=to_ufixed(0.05,8,4)*to_ufixed(compteur1,8,4); output<=realnumber(7 downto 0); Where output only wants the bits that are not behind the fixed point, and being an unisgned(7 downto 0).

richardhead

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03-08-2018 12:42 PM

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Registered:
08-01-2012

Take a read of synthesis UG901, https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug901-vivado-synthesis.pdf, specifically the section on VHDL 2008. It explains first you need to add the fixed library to your project (provided in Vivado as a '93 compatible version)

you need to include the library in your code (assuming comptear is unsigned)

use ieee.fixed_pkg.all;

realnumber<=to_ufixed(0.05,8,4)*to_ufixed(compteur1,8,4); output<=unsigned( realnumber(7 downto 0) );

But why make everything unsigned when you could just stick with ufixed?

sebs

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03-08-2018 03:08 PM

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03-07-2018

Re: Multiplication of fixed point by an integer

The thing is that I want to send afterwards the integer that ends up as an output in STD_LOGIC_VECTOR. I made it unsigned but I think that I could use directly STD_LOGIC_VECTOR. Thank you very much, now my sintax is good I only need to change something so it can synthesize. In case someone needs to see how the code ended up being so they can get some ideas of how to use the ufix or find the solution of the synthesize problem here it is. The problem is in the Conversión part, but syntax is okay (it says that when doing: realnumber<=to_ufixed(0.05,8,4)*to_ufixed(compteur1,8,4); that Expression has 10 elements ; expected 12.) Thanks for the previous help to everyone and if someone can help with this problem it would also be of great help.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library ieee_proposed; use ieee_proposed.fixed_pkg.all; entity ADC is port(PWM_in: in STD_LOGIC; clk: in STD_LOGIC; Digital: out STD_LOGIC_VECTOR(7 downto 0); Finish: out STD_LOGIC ); end ADC; architecture Behavioral of ADC is type ADC_Machine is(Data_Reception, Conversion, Finir); signal state, next_state: ADC_Machine; signal period: integer:=0; signal compteur1: integer:=0; signal output: STD_LOGIC_VECTOR(7 downto 0):=(others=>'0'); signal realnumber: ufixed(7 downto -4) :=(others=>'0'); begin GeneralPro:process(clk) begin if(rising_edge(clk)) then state<=next_state; end if; end process; Machine:process(PWM_in,clk) begin case (state) is when Data_Reception=> Finish<='0'; if(rising_edge(clk))then period<=period+1; end if; if(PWM_in='1' and rising_edge(clk)) then compteur1<=compteur1+1; end if; if(period=200) then next_state<=Conversion; else next_state<=state; end if; when Conversion => Finish<='0'; realnumber<=to_ufixed(0.05,8,4)*to_ufixed(compteur1,8,4); output<=STD_LOGIC_VECTOR(realnumber(7 downto 0)); next_state<=Finir; when Finir=> Finish<='1'; compteur1<=0; period<=0; next_state<=Data_Reception; end case; end process; Digital<=output; end Behavioral;

richardhead

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03-09-2018 12:05 AM

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Registered:
08-01-2012

Re: Multiplication of fixed point by an integer

The problem is here:

realnumber<=to_ufixed(0.05,8,4)*to_ufixed(compteur1,8,4);

Realnumber is only 12 bits, but a 12bit * 12bit = 24 result (specifically 16 integer and 8 fraction).

so you should either declare:

signal realnumber : ufixed(23 downto -7);

or use the resize function:

realnumber<= resize( to_ufixed(0.05,8,4)*to_ufixed(compteur1,8,4), 8, 4);

Resize will NOT round or saturate the result. So the first option may be preferable.

sebs

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03-09-2018 01:17 AM

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03-07-2018

Re: Multiplication of fixed point by an integer