Multisource errors in some Verilog processes with more than one assignment in the same block
The following code illustrates the problem in XST10.1.03
Although full_histo_addr is only assigned in one always block it shows up as a multisource
with one connection to GND if I uncomment the code near the top. The final else clause
was added to work around the error. As noted below the similar but simpler code for
full_histo_clear did not cause a similar error.
always @ (posedge clk_in or posedge rst_in) begin : LaneBlock integer i; // local loop variable if (rst_in) begin full_histo_raddr <= 0; full_histo_clear <= 0; end else begin // Default to zero for cases not covered below // The following line created a "multi-source" error in XST // This is a bug. Interestingly the line // after this does not produce the same error. // full_histo_raddr <= 0; // full_histo_clear <= 0; for (i = 0;i < 10;i = i + 1) begin if (cl1_lanes[i]) begin full_histo_clear[i] <= cl1_clear; full_histo_raddr[i*8 +: 8] <= cl1_raddr; end else if (cl2_lanes[i]) begin full_histo_clear[i] <= cl2_clear; full_histo_raddr[i*8 +: 8] <= cl2_raddr; end else if (cl3_lanes[i]) begin full_histo_clear[i] <= cl3_clear; full_histo_raddr[i*8 +: 8] <= cl3_raddr; end // Originally there was no "else" clause and I expected // this to be covered by the pre-assignments above. That // caused "multi-source" errors as noted above. else begin full_histo_clear[i] <= 0; full_histo_raddr[i*8 +: 8] <= 0; end end end end
This thread shows another example of the same problem, this time in a combinatorial