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mat075
Newbie
Newbie
3,714 Views
Registered: ‎07-12-2017

My clk input is still 100MHz (gclk)

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Hello everybody !

First of all, I'm a beginner in FPGA so please be nice with me :) !

My problem is very simple but I tried a lot of things to solve it but I still can't manage it. I use an Artix - 7. I want to modify the internal clock (GCLK pin E3 bank 35 100MHz). I launched synthesis Design, after I edited "edit timing contraints" to modify the clock at 50Khz.. To verify if it's good, I launched " Constraints Wizard " and  "Report clock Network "everything is ok. But after program my device ( thanks to .bit file) I still have 100MHz in my clk ouput (the clk input is directly connect to this ouput to see on the scpoe the signal) whereas I want 50Khz.. I checked my xdc File and the frequency is 50KHz. No erros in  log file.

What can I do ?

(Sorry for my bad English ) 

xdc_clock.JPG
report clock.JPG
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florentw
Moderator
Moderator
6,206 Views
Registered: ‎11-09-2015

Hi @mat075,

 

A constraint is only to inform vivado about what you have. So if you just create a constraint for 50KHz, the tool will just think you have a 50KHz clock while in fact you still have a 100MHz clock (this is what you see).

 

To really create a new clock you would need to use an MMCM or a PLL. The easy way for this is to use a clocking wizard IP.

But you won't be able to go as low as 50kHz so you wil have to do a clock divider in vhdl or verilog.

 

Kind Regards,

 

Florent

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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florentw
Moderator
Moderator
6,207 Views
Registered: ‎11-09-2015

Hi @mat075,

 

A constraint is only to inform vivado about what you have. So if you just create a constraint for 50KHz, the tool will just think you have a 50KHz clock while in fact you still have a 100MHz clock (this is what you see).

 

To really create a new clock you would need to use an MMCM or a PLL. The easy way for this is to use a clocking wizard IP.

But you won't be able to go as low as 50kHz so you wil have to do a clock divider in vhdl or verilog.

 

Kind Regards,

 

Florent

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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mat075
Newbie
Newbie
3,689 Views
Registered: ‎07-12-2017

Hi @florentw !

 

Thanks for your help. Do you have some documents or links to inform me about "cloking wizard IP" ?

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reshmaakhil
Explorer
Explorer
3,688 Views
Registered: ‎12-05-2016

hi @mat075,

 

you can use a clock divider. 

 

it will work.

 

regards,

reshma

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yenigal
Xilinx Employee
Xilinx Employee
3,684 Views
Registered: ‎02-06-2013

Hi

 

check below links

https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_4/pg065-clk-wiz.pdf

 

https://www.xilinx.com/products/intellectual-property/clocking_wizard.html

 

Regards,
Satish

Regards,

Satish

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mat075
Newbie
Newbie
3,681 Views
Registered: ‎07-12-2017
What do you mean ?
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florentw
Moderator
Moderator
3,668 Views
Registered: ‎11-09-2015

Hi @mat075,

 

The min clock you will be able to output with the clocking wizard on Artix-7 is a clock 4.69MHz (it comes from the limit on the MMCM).

 

To get a 50kHz you will have to divide the clock by ~100.

 

The simplest way to do it is to do a clock divider in RTL (VHDL/Verilog) with a counter. Something like (in VHDL):

...

cnt_sig : std_logic_vector(6 downto 0) := (others => '0');

clk_out : std_logic;

...

process(clk)

begin

   if(rising_edge(clk)) then

      cnt_sig <= cnt_sig + '1';

      if(cnt_sig = "1100100") then -- if = 100

           clk_out <= '1';

      else

           clk_out <= '0';

      end if;

   end if;

end process;

 

Then when you will have more experience, the best way is to use a BUFGCE:

BUFGCE.JPG

But again this will be future improvements when you will have more experience in FPGA.

 

Kind Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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mat075
Newbie
Newbie
3,663 Views
Registered: ‎07-12-2017
That's very clear now !

Thank you very much guys.
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