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Observer
Observer
315 Views
Registered: ‎02-12-2020

My code works on behavioral simulation but not post synthesis functional simulation

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Here is my code and I give constraints as follows

create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 1} [get_ports { clk }];#set

As you know, it is possible to debug in RTL Simulation. But after synthesis, I cannot identify the variable.

Can you give me some tips or solutions to do debug?

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Xilinx Employee
Xilinx Employee
296 Views
Registered: ‎06-14-2018

Re: My code works on behavioral simulation but not post synthesis functional simulation

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Hi @laurent01 ,

Could you provide more information, is this logic bug you are observing in post-synthesis functional simulation ?

Also could you provide testbench/stimulus you are applying to RTL and post-synthesis simulation.

I have tried formal check RTL vs Netlist (2019.2 & 7 series), result is equivalent/PASS. 

Thanks,

Ajay 

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Xilinx Employee
Xilinx Employee
297 Views
Registered: ‎06-14-2018

Re: My code works on behavioral simulation but not post synthesis functional simulation

Jump to solution

Hi @laurent01 ,

Could you provide more information, is this logic bug you are observing in post-synthesis functional simulation ?

Also could you provide testbench/stimulus you are applying to RTL and post-synthesis simulation.

I have tried formal check RTL vs Netlist (2019.2 & 7 series), result is equivalent/PASS. 

Thanks,

Ajay 

View solution in original post

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Observer
Observer
279 Views
Registered: ‎02-12-2020

Re: My code works on behavioral simulation but not post synthesis functional simulation

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Thanks, I found the error in my testbench.
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