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beep7886
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Registered: ‎06-11-2013

NEED HELP WITH $readmemb for synthesis

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Hey guys I am just practicing writing to memory on the Artix 7 AC701 evaluation board.  I wanted to write a program that would read a file into memory and than turn on the led"s on the board in whatever pattern the file suggests.  Synthesis and Implementation passed, but when I try and run the program on the device, the lights don't turn on.  Everything seems to be working fine in the test bench.  Is there a certain place I should be storing the file for synthesis.  Please help.

 

module mem(input clk,reset,output[3:0]led);
integer data; // pointer to data file
integer count=0; //counter
integer j=0; // options for different light patterns
reg [3:0]ledr=1'b0;
wire [3:0]led=1'b0;
//12 location, 1 bit memory
reg [0:0]memory1 [0:11];
// before anything else, load memory using the data in the file
initial begin
$readmemb("data.txt",memory1,0,11);
end
//start the clock cycle
always@(posedge clk)
begin
if(reset==1)//if reset
begin
ledr[0]=1'b0;
ledr[1]=1'b0;
ledr[2]=1'b0;
ledr[3]=1'b0;
count=0;
end
else // if reset is not pushed than begin counting and start turning on lights
begin
if (count<=3000000)
begin
count=count+1;
end
if (count>3000000)
begin
if(j==0) // option 1
begin
ledr[0]=memory1[0];
ledr[1]=memory1[1];
ledr[2]=memory1[2];
ledr[3]=memory1[3];
count=0;
end
if(j==1) // option 2
begin
ledr[0]=memory1[4];
ledr[1]=memory1[5];
ledr[2]=memory1[6];
ledr[3]=memory1[7];
count=0;
end
if(j==2) // option 3
begin
ledr[0]=memory1[8];
ledr[1]=memory1[9];
ledr[2]=memory1[10];
ledr[3]=memory1[11];
count=0;
end
end
j=j+1; // reset the option control back to zero
if(j>2)
begin
j=0;
end
end
end
// assign the register values to the wire LED's
assign led[0]=ledr[0];
assign led[1]=ledr[1];
assign led[2]=ledr[2];
assign led[3]=ledr[3];
endmodule

1 Solution

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gszakacs
Instructor
Instructor
15,944 Views
Registered: ‎08-14-2007

@beep7886 wrote:

Im getting this as one of my warnings

 

  • [Synth 8-2898] ignoring malformed $readmem task: invalid memory name ["D:/xilinx/xilinx_programs/mem_practice/mem_practice.srcs/sources_1/new/mem.v":32]  

Well, that seems to be the problem.  XST is ignoring the $readmemb altogether.  Wasn't your memory called

"memory1" when you posted this originally?

 

Have you tried to remove the path and place "data.txt" in your current project directory?

-- Gabor

View solution in original post

11 Replies
gszakacs
Instructor
Instructor
12,821 Views
Registered: ‎08-14-2007

Did you get any warnings from synthesis about the file you tried to load?

 

Normally with no other path information, the file should be placed in the project directory.

You can use relative path information to get the file from another location.  For example

I usually have a directory structure like:

 

Proj_name

  constraints

  source

  sim

  cores

  synth

 

In this case my "project directory" for ISE is Proj_name/synth and my source files,

including any initialization files would be in Proj_name/source.  So I could use $readmemb

like:

 

initial begin

  $readmemb ("../source/init10.txt",memory);

end

 

 

I haven't tried partial initialization of memory using $readmemb or $readmemh recently,

but I know it didn't used to work for earlier versions of ISE.  The default is to read the entire

file, which is expected to have exactly the number of elements required by the memory array.

Also, in earlier versions of ISE (haven't checked this recently) XST liked to have just one

element on each line of the text file like:

 

10110001

01011011

11110010

 

etc.

 

HTH

-- Gabor
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beep7886
Visitor
Visitor
12,815 Views
Registered: ‎06-11-2013

Thanks for the response!!

I have tried to make it simple with the path, so I moved it to the root of my C drive.

 

initial begin

$readmemb("C:/data.txt",memory);

end

 

I also made sure to format the file like you suggested with one element per line, but i still am not getting these LED's to turn on.

 

In my test bench it appears that the memory register is loading all the data correctly, for some reason it is not working on the hardware.

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beep7886
Visitor
Visitor
12,814 Views
Registered: ‎06-11-2013

Im getting this as one of my warnings

 

  • [Synth 8-2898] ignoring malformed $readmem task: invalid memory name ["D:/xilinx/xilinx_programs/mem_practice/mem_practice.srcs/sources_1/new/mem.v":32]  
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gszakacs
Instructor
Instructor
15,945 Views
Registered: ‎08-14-2007

@beep7886 wrote:

Im getting this as one of my warnings

 

  • [Synth 8-2898] ignoring malformed $readmem task: invalid memory name ["D:/xilinx/xilinx_programs/mem_practice/mem_practice.srcs/sources_1/new/mem.v":32]  

Well, that seems to be the problem.  XST is ignoring the $readmemb altogether.  Wasn't your memory called

"memory1" when you posted this originally?

 

Have you tried to remove the path and place "data.txt" in your current project directory?

-- Gabor

View solution in original post

beep7886
Visitor
Visitor
12,800 Views
Registered: ‎06-11-2013

Yeah sorry for the typo, memory1 is correct.

 

My code now reads:

reg [0:0]memory1 [0:11];
// before anything else, load memory using the data in the file
initial begin
$readmemb("data.txt",memory1);
end

 

....................................................................................................................................

the file looks like:

1
0
0
1
1
0
1
0
1
1
1
1

......................................................................................................

My project name is mem_practice

For simulation I had to stick the file into mem_practice.sim/sim_1/behav/data.txt

Are you saying that for synthesis I should just have the data.txt file in the root mem_practice folder??

Thanks again for the help, and sorry for all these questions I am rather new to fpga programming.

By the way I am using Vivado 13.1 if that makes a difference.

 

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beep7886
Visitor
Visitor
12,791 Views
Registered: ‎06-11-2013

I have now place the data.txt file in just about every folder possible in the project and I am still geting the same error

 

  • [Synth 8-2898] ignoring malformed $readmem task: invalid memory name ["D:/xilinx/xilinx_programs/mem_practice/mem_practice.srcs/sources_1/new/mem.v":32]
  • [Synth 8-3848] Net memory1[8] in module/entity mem does not have driver.
  • [Synth 8-3848] Net memory1[9] in module/entity mem does not have driver.
  • [Synth 8-3848] Net memory1[10] in module/entity mem does not have driver.
  • [Synth 8-3848] Net memory1[11] in module/entity mem does not have driver.
  • [Synth 8-3848] Net memory1[4] in module/entity mem does not have driver.
  • [Synth 8-3848] Net memory1[5] in module/entity mem does not have driver.
  • [Synth 8-3848] Net memory1[6] in module/entity mem does not have driver.
  • [Synth 8-3848] Net memory1[7] in module/entity mem does not have driver.
  • [Synth 8-3848] Net memory1[0] in module/entity mem does not have driver.
  • [Synth 8-3848] Net memory1[1] in module/entity mem does not have driver.
  • [Synth 8-3848] Net memory1[2] in module/entity mem does not have driver.
  • [Synth 8-3848] Net memory1[3] in module/entity mem does not have driver.  
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gszakacs
Instructor
Instructor
12,782 Views
Registered: ‎08-14-2007

Vivado may make a difference.  I normally use ISE.

 

In ISE 14.5, the original post with the exception of this line:

 

wire [3:0]led=1'b0;

 

seems to work OK.

 

I made a new project with just this module and data.txt in the project directory.  After removing that

line the only warning I get is:

 

HDLCompiler:872 - "C:\Projects\junk\MemInitTest\mem.v" Line 12: Using initial value of memory1 since it is never assigned

 

which seems to be bad, but actually it's normal for a ROM memory.  It just means there are no assignments

to memory1 after the initial block (i.e. in an always block).

-- Gabor
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beep7886
Visitor
Visitor
12,771 Views
Registered: ‎06-11-2013

I moved my project over to ise 14.4 to see if that fixed the problem,

 

Elaborating module <rom>.
ERROR:HDLCompiler:990 - "C:\Users\NavLabs\Desktop\XILINX\nav_science\rom_practice\rom.v" Line 33: Cannot open file data.txt
Module rom remains a blackbox, due to errors in its contents
WARNING:HDLCompiler:1499 - "C:\Users\NavLabs\Desktop\XILINX\nav_science\rom_practice\rom.v" Line 21: Empty module <rom> remains a black box.
-->

for some reason I am not able to open up the file

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gszakacs
Instructor
Instructor
12,756 Views
Registered: ‎08-14-2007

Just to be clear.  In ISE, the "project" directory is the one where the .xise file is stored.  You placed "data.txt" in that directory?

-- Gabor
beep7886
Visitor
Visitor
5,557 Views
Registered: ‎06-11-2013

That fixed it!!!

Thank you so much for the help, you saved me a lot of time, and a lot of headaches.  Thanks again.

-Brandon

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hina21
Newbie
Newbie
3,244 Views
Registered: ‎07-20-2018

i have also the same issue with loading text file can you plz help me?

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