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kidrahiterpu
Visitor
Visitor
398 Views
Registered: ‎05-13-2021

NaN in VHDL

In my VHDL code i want to compare a value with NaN and then proceed with further operations.

For example 

if (x is not NaN) then

.....

How I can do this such that the code is synthesizable?

 

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4 Replies
richardhead
Scholar
Scholar
368 Views
Registered: ‎08-01-2012

You Dont show what types are being used. Real type is not synthesisable. Float types from float_pkg will not produce optimal logic.  You should be using xilinx float ip cores. But why are you using float at all? Fpgas are not architected for float, they work best with fixed point.

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kidrahiterpu
Visitor
Visitor
344 Views
Registered: ‎05-13-2021

I am working with fixed point data.

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richardhead
Scholar
Scholar
332 Views
Registered: ‎08-01-2012

Fixed point has no representation of NaN. If you are trying to catch a divide by 0, you will have to track that yourself.

apetley
Xilinx Employee
Xilinx Employee
246 Views
Registered: ‎06-14-2018

Hi @kidrahiterpu ,

Further, Vivado flags Critical Warning if divide by zero scenario is encountered.

CRITICAL WARNING: [Synth 8-5821] Potential divide by zero in module top

Thanks,

Ajay

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