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mofana
Visitor
Visitor
10,488 Views
Registered: ‎05-02-2016

Name index used in constraints file

Hi,

 

I am having a vectorized input, that is indexed not by numbers, but by enumerators. How can I use same naming in the xdc file? Vivado complains that the names are not supported:

 

library:

type diffrential_t is (p, n);
type std_logic_dif is array (diffrential_t range p to n) of std_logic;

 

entity:

  dco: in std_logic_dif;

 

xdc file:

set_property PACKAGE_PIN  AB4 [get_ports dco[p]]

 

I encounter with such error:

Command 'p' is not supported in the xdc constraint file.

 

Note: I want to use namings, but not index numbers to avoid confusion and keep it flexible.

P.S. Can I define such constraints, using VHDL attributes?

 

Thanks,

 

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9 Replies
vemulad
Xilinx Employee
Xilinx Employee
10,484 Views
Registered: ‎09-20-2012

Hi @mofana

 

Try below instead (add flower braces around port name)

 

set_property PACKAGE_PIN  AB4 [get_ports {dco[p]}]

Thanks,
Deepika.
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mofana
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10,479 Views
Registered: ‎05-02-2016

Thank you Deepika,

 

I am getting the following "critical warning", after applying your changes:

'set_property' expects at least one object.

 

Seems like it cannot find the port!

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vemulad
Xilinx Employee
Xilinx Employee
10,477 Views
Registered: ‎09-20-2012

Hi @mofana

 

Can you open synthesized design and run get_ports command from tcl console? Please share the output here.

Thanks,
Deepika.
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mofana
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10,475 Views
Registered: ‎05-02-2016

I think that is the problem. The synthesis tool, converts, the enumerator values to integers by itself:

 

dco[0] dco[1] ...

 

Can I define some variables in xdc file, and use that as the index? something like:

set p 0

set n 1

get_ports {dco[$p]}

 

 

 

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avrumw
Expert
Expert
10,449 Views
Registered: ‎01-23-2009

You can use variables in your xdc files, so the syntax you have for defining $p and $n should work.

 

But, I suspect that this is pretty much your only solution - you are correct that synthesis replaces enumerated types with an underlying numeric representation - the enumerated type differential_t (and its enumeration values) are lost after synthesis.

 

Avrum

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geoffbarnes
Explorer
Explorer
10,413 Views
Registered: ‎09-07-2011

Can we in general rely on p=0, n=1?

 

Might be just as readable to use something like:

 

constant n : integer := 1;

constant p : integer := 0;

subtype std_logic_diff is std_logic_vector(p to n);

 

dco : in std_logic_diff;

 

Then use "set p 0" etc, in xdc file.

 

 

Or....

 

I'm pretty sure record member names are preserved.  Can try:

  type std_logic_diff is record

        p : std_logic;

        n : std_logic;

   End record;

 

The record members should be visible as dco[p] and dco[n] in the xdc file.

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mofana
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Registered: ‎05-02-2016

Thank you @geoffbarnes and @avrumw. The 's solution to use records works fine.

 

However, using constants, I cannot access variables in xdc!!

 

set p 0

 0

get_ports {dco[$p]}
 WARNING: [Vivado 12-584] No ports matched 'dco[$p]'.

get_ports {dco[0]}
 dco[0]

 

And I have to use constants. Because I need to access them in my VHDL code as an array (to iterate thorough), but as record.

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mofana
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10,395 Views
Registered: ‎05-02-2016

I removed the braces, and now this is the problem:
[Designutils 20-1307] Command '$p' is not supported in the xdc constraint file.
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avrumw
Expert
Expert
10,372 Views
Registered: ‎01-23-2009

With the hard quotes (braces) what you saw is expected - inside hard quotes commands and variables are not expanded.

 

I would have expected it to work without any quotes, since it is a single string...

 

But you can try with soft quotes ("") - that might work.

 

get_port "dco[$p]"

 

Avrum

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