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Observer sarmad_wahab
Observer
471 Views
Registered: ‎11-07-2016

Need Advice and Suggestion

Hello Everyone,

                            I need a friendly suggestion and advice because i am really broken and disappointed by fpga's. Before that i was a huge fan of Fpga's, i have my own fpga spartan 6 on which i have developed alot of projects. Almost ten months ago i started project in university while pursuing master degree, the title was to design a wrapper between wishbone slave interface and DDR3 SDRAM Memory controller Fpga 7 series Artix. I wrote synthesizable code (Verified by Vivado and ISE synthesis tool, it has no warnings, crtical errors etc) for wrapper and tested it with standard testbenches provided by xilinx (Vivado Core Generator). Everything was working perfect and fine. My work was a small portion of big project. Wishbone slave interface is connected to OpenRisc processor designed by some other group/person (Processor is generating data and read/write instructions). When me and my supervisor implemented whole project on Fpga 7 series artix, Fpga stops responding after successful thousands read/write operations. After investigating it with Integrated Logic Analyzer (ILA) we came to know that DDR3 memory controller de asserts two important signals (i_ddr3_app_ready & i_ddr3_app_wdf_ready) indicating that DDR3 memory controller is not ready to accept further commands. And with ILA we have also observed that exceptions are being generated by OpenRisc processor. I am continiously blamed by my supervisor that there is problem with my wrapper. My question is that, VHDL code which is synthesizable and tested with standard testbenches can cause hardware failure ?. If it is not necessary that every synthesizable code will work fine on fpga then why fpga's are being used in market.?

 

Best Regards,

Sarmad Wahab  

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Scholar hbucher
Scholar
463 Views
Registered: ‎03-22-2016

Re: Need Advice and Suggestion

@sarmad_wahab Addressing the last sentence -

Just because a program compiles, it does not mean that it is bug-free. That was the goal of the ADA language by the way.  Unfortunately it does not work like that. This is true for any electronic system - software or hardware.

 

Just by looking at your big text it sounds more like a rant that no one will want to take part on. Perhaps reddit.com/r/fpga would be the proper place for it.

 

Now, if you are asking for help, you gave not enough details. I advise you to break down the problem to the smallest piece conceivable and share screenshots. Ask specific questions - there are tons of skilled people around here ready to help you out.

 

 

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