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Lex789
Newbie
Newbie
637 Views
Registered: ‎05-19-2020

Net declaration assignment for unpacked array in SystemVerilog

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Hi.

I think I've found a bug in SystemVerilog elaboration of Vivado 2019.2. As I didn't find a bug tracker, I thought I'd post it here.

module MyMemory(
    input wire logic[6:0] readAddr_i [2],
    output logic[5:0] data_o,
    output logic tag_o
);

    typedef struct packed {
        logic tag;
        logic[5:0] addr;
    } MemoryAddress;
    
    wire MemoryAddress readAddr [2] = readAddr_i;
    
    always_comb begin
        data_o = 0;
        tag_o = 0;
        for(int i = 0; i < 2; i++) begin
            data_o = data_o + readAddr[i].addr;
            tag_o = tag_o | readAddr[i].tag;
        end
    end

endmodule

The problem is the declaration assignment of readAddr. When looking at the elaborated design, Vivado seems to mix components of the struct and the unpacked array dimension. When it is separated in a declaration statement and a continuous assignment, the result is correct:

wire MemoryAddress readAddr [2];
assign readAddr = readAddr_i;

Best regards,
Alexander

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pulim
Xilinx Employee
Xilinx Employee
617 Views
Registered: ‎02-16-2014

Hi @Lex789 

 

Thanks for reporting this issue.

I reported this issue to get it fixed in future releases of vivado.

 

Thanks,

Manusha

View solution in original post

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pulim
Xilinx Employee
Xilinx Employee
618 Views
Registered: ‎02-16-2014

Hi @Lex789 

 

Thanks for reporting this issue.

I reported this issue to get it fixed in future releases of vivado.

 

Thanks,

Manusha

View solution in original post

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