Nets missing in Netlist - Vivado 2014.2

[anm]

Hi,

I am using Vivado 2014.2.

I have made a project which I have tested on my Kintex 7 - xc7k160tfbg676 FPGA and it was working well.
Today I tried to add to my project an MMCME2_BASE. I accomplished to instantiate it (or so I think) and I Synthesized my project successfully (as I was only getting the usual warnings that I was expecting to get).
Nevertheless when I opened Synthesis, in Netlist the majority of my Nets (that derived from components inside my project) were missing!
I rolled back to a previous working version of my project, I synthesized again, but the problem remained. The Nets are still missing, so I am not able to debug them using ILA. That tells me that the addition of the MMCM was not the problem.
I am assuming that Vivado for some reason removes some of the components inside my project, but the strange thing is I don't get such kind of warning (I repeat, I only get the usual warnings I am expecting to get).

Any ideas on what is happening?

Nassos

[vijayak]

Hi @anm

1) Did you try running post synthesis simulation to confirm functionality of your module?

2) You can use dont_touch attribute if you want the tool not to trim the portions of your logic.

3) I suggest you to use the latest version of Vivado (2016.4)for better results.

Refer to https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug901-vivado-synthesis.pdf for details on dont_touch usage.

[florentw]

Hi @anm,

Unused nets are removed during synthesis. You may want to have a look to the synthesis log (<proj_neame>.runs/synth_1/...log). See if the nets are mentioned.

Hope that helps

Regards,

Florent

[anm]

@florentw
Already checked it but not a sign of the removed networks.
@vijayak
Thank you for the useful 'dont_touch' atribute. Not able to upgrade, cause I use Vivado through a University server.

I made a new project with the same VHD files, and now it seems to work well. Maybe something with the 'debugg' and 'undebugg' of the nets I used for the Debugg Core, messed the project.
Thank you both for your quick replies.

[anm · Accepted solution]

@florentw
@vijayak

Excuse my naive approach of my own matter. I found out today that by using the Tcl command "set_msg_config"  I could be able to see any trimmed Synthesis Warnings. Indeed there were about ~1300 trimmed warnings of the components that were missing (as @florentw mentioned) but not any actual information on why these components were removed.
I thought that was strange so I started googling and I stumbled upon this useful comment by @muzaffer:

https://forums.xilinx.com/t5/Synthesis/Sequential-element-is-unused-and-will-be-removed-from-module/m-p/545377/highlight/true#M12797

I decided to enter the Synthesis Settings and I there I found the option "-flatten_hierarchy*". I don't know if by deafault it is on "rebuilt", but for me it was. I turned it to "none" and...to my suprise the nets/components were back!!
I also enabled the option "-keep_equivalent_registers*".

Thanks again for the support.

Kind regards,
Nassos

[anm]

@florentw
@vijayak

On a  third look of my design, I noticed that by turning "-flatten_hierarchy*" from "rebuilt" to "none", the Implementation stage takes a lot longer to be accomplished and when it does, the percentage of used LUTs and FFs is significally increased in the Post-Implementation Graph. Also the resulting design didn't have the initial functionality it used to. So I started to suspect that there was a flaw in my own design that made Vivado trim my components and NOT the Synthesis Settings.
I figured that a small change I had made in a component of mine, kept some of the outputs stable to a single value (probably '0'), so when Vivado trimmed those outputs and removed that component, a chain reaction started and all the components connected to the removed component, were also trimmed. 
When I fixed that little flaw, my design started to work as intented (all Components/Nets were present at Netlist) with the Synthesis Settigns rolled back to "-flatten_hierarchy*" = "none" and "-keep_equivalent_registers*" UNchecked.

P.S.
I understand that my previous answer did solve my problem with the missing Nets from Netlist, but I think THIS answer is more appropriate as solution from the point that it resolves also the proper functionality of the design.
I leave it to the Moderators to decide if the accepted solution should change.