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trupti.chavan
Visitor
Visitor
776 Views
Registered: ‎03-18-2019

Not able to synthesize code in Verilog 2001 - IEEE Std 1364-2001

Hi,

I am trying to sithesize below code in vivado 2018.2. Please find the attached code with filenames.

file: param.v    

parameter LENGTH = 8,

parameter LSB =1

 

file: main_cnt.v

module main_cnt #(

       `include "param.v",

        parameter FIFO = 1 ) (

input clk,

input resetn,

... different IO );

<  module_logic  >

endmodule

 

 

I am trying to define parameters in a file and include parameter file by `include command. In ideal case, its expected to work, as `include will replace all content of included file at called location.

same code is getting synthesized on synopsis DC. But Vivado is throwing errors for me. How should I synthesize above code in vivado 2018.2.   

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2 Replies
aschule
Xilinx Employee
Xilinx Employee
741 Views
Registered: ‎04-19-2010

What is the exact error that you are getting?  Also, how did you set up your project to run?  I made a quick testcase that looks like yours, and this worked fine for me.  My guess is that there might be something in how this was set up.

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trupti.chavan
Visitor
Visitor
703 Views
Registered: ‎03-18-2019

Please find attached .v files. Also attached project.

I created a project and added main_cnt.v in project, set as top module.

As I have `include in main_cnt.v, params.v should have been automatically get added under non module sources But its under  syntax error file and giving error for line 23 in param.v( parameter LENGTH = 5 ).

Also Its showing warning in main_cnt.v as `include directive not isolated on its own line.

 

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