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frafraf
Observer
Observer
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Registered: ‎11-06-2018

One or two process state machines, does it affect synthesis?

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Hi, I have read that the two process state machine leads to a more optimized synthesis, and I assume the reason is that fewer control signals are utilized when using this style. That is, we are manually converting control signals (clk enables, etc) to logic placed on the data path instead of control path. BUT, considering the good deal of optimizations done by the synthesis tool, does it really make any difference regarding synthesis results whether we use a single or two separate always blocks for implementing state machines? I have a feeling that this recommendations is kind of old, and today the synthesis tool takes good care of all optimizations of this sort.

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richardhead
Scholar
Scholar
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Registered: ‎08-01-2012

From my understanding, the two process state machine style comes from times of old (very old, as the following has never been an issue for me in 16 years). Back in synthesis infancy, tools struggled to create logic chains inside a clocked process, and hence it was a requirement that logic and registers were placed in separate processes. For some reason, this style has persisted only with state machines, and it seems to be the only old design style that wont go away.

Synthesis tools have evolved in the last 16 years (and more). They are now very good at generating logic and registers from any old code that you can throw at it (good and bad). While in some instances, some engineers may be able to get some performance enhancements from hand crafted two process style code, in the majority of cases, you likely wont and readability and understaning for future users usually suffers. LUTS and registers are basically free nowadays, so sacrificing a few luts and a few MHz of FMAX to more reliable, readable code is usually one worth making.

Another problem is that a lot of teachers of VHDL at unis have not been in the industry for a long time, and still preach the design patterns from their 20 year old text books.

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

Nope,

Older books tend to each two and three process state machines, as well as mealy and more,

  IMHO , in reality, 

   apart from at school, you will not see pure meley / more machines.

The tools take your code, and synthesise it

    think of if you write C code, you would be surprised to see that code exactly implemented in the ASM code,

   

Just write single process state machines,

    you have much lower probability of making latches,

      which you don't want

 

This used to matter, in the days FSM were made out of logic chips, or even the simple CPLDs ,

   

but not in FPGAs ,

 

Remember , if you exepriment how the tools work,

    they run to meet your constraints and stop,

so if you make two versions of  design, one in a two process , one in a single process,

     they could well take up different amount of resources,

   till you start pushing the constraints, then the tools are not going to do much if any optimisation.

 

   

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
richardhead
Scholar
Scholar
472 Views
Registered: ‎08-01-2012

From my understanding, the two process state machine style comes from times of old (very old, as the following has never been an issue for me in 16 years). Back in synthesis infancy, tools struggled to create logic chains inside a clocked process, and hence it was a requirement that logic and registers were placed in separate processes. For some reason, this style has persisted only with state machines, and it seems to be the only old design style that wont go away.

Synthesis tools have evolved in the last 16 years (and more). They are now very good at generating logic and registers from any old code that you can throw at it (good and bad). While in some instances, some engineers may be able to get some performance enhancements from hand crafted two process style code, in the majority of cases, you likely wont and readability and understaning for future users usually suffers. LUTS and registers are basically free nowadays, so sacrificing a few luts and a few MHz of FMAX to more reliable, readable code is usually one worth making.

Another problem is that a lot of teachers of VHDL at unis have not been in the industry for a long time, and still preach the design patterns from their 20 year old text books.

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frafraf
Observer
Observer
349 Views
Registered: ‎11-06-2018
Thank you very much for your detailed and to the point replies, drjohnsmith and richardhead. I got the point. It's better to use the simple, single process state machines which are less prone to cause mistakes and misunderstandings, considering the optimization capabilities of today's synthesis tools.