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hgomersall
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Registered: ‎12-27-2014

Optimisation of if statements?

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For a simple logic if statement like the following:

always @(posedge clock) begin: FOO_CASE_ADD
    if (flag) begin
        output <= (A + B);
    end
    else begin
        output <= (C + D);
    end
end

(or VHDL if you'd prefer)

 

FOO_CASE_ADD: process (clock) is
begin
    if rising_edge(clock) then
        if bool(flag) then
            output <= (A + B);
        else
            output <= (C + D);
        end if;
    end if;
end process FOO_CASE_ADD;

How does Vivado optimize this?

 

In principle, only a single addition should happen, but a naive implementation might have two adders that always run with the output multiplexed.

 

I vaguely aware of using the power optimiser to do register clock gating, but I don't know how much of this just happens automatically. I mean, the above could be implemented with the inputs being multiplexed rather than the output, which would be great, but can I assume that will happen?

 

Obviously, this is a trivial case, but I'm trying to understand more about what optimizations are done at elaboration and synthesis time to know what I need to do in my own code. Is there a list of optimizations that are done somewhere?

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jmcclusk
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Registered: ‎02-24-2014

This is controlled by the synthesis option  "-resource_sharing" in Vivado.   The default value is "auto".   In general, if Vivado detects this kind of optimization, it will swap the order of the multiplexers and adders to minimize the logic.    Synplicity pioneered this optimization about 15 years ago. 

Don't forget to close a thread when possible by accepting a post as a solution.

View solution in original post

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richardhead
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Registered: ‎08-01-2012

But you have written it as 2 separate adders that are then muxed. If you wanted to use a single adder, then you should mux the inputs to the adder.

 

--vhdl 2008 syntax
process(clk)
variable add0, add1 : output'subtype; beign if rising_edge(clk) then add0 := a when flag = '1' else c; add1 := b when flag = '1' else d; output <= add0 + add1; end if; end process;

Afaik, it cannot change your logic, but it can merge registers/rams that have the same bahaviour. And move registers along a pipeline to improve timing based on register retiming. But it cannot change your circuit functionality.

 

Its obvious to the user that this could take one of two logic forms, but not necessarily obvious to a synth tool. 

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hgomersall
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Registered: ‎12-27-2014
Right, that's the question - how clever is the synth optimizer? The two implementations are absolutely equivalent at the RTL level, so it _could_ simplify the logic.

c.f. everyone expects simple boolean operations to be reduced to their minimal logical equivalent.
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richardhead
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Registered: ‎08-01-2012

Id argue that they are not absolutely equivalent. They are only equivolent because you know they can be modified to get similar results. They may have different timing results that may be needed. A user may want to lock down one of the two adders. If the synth started optimising it, it would make this kind of thing impossible or very difficult with different settings needed for different parts of the design.

 

You need to give engineer some responsibility for the code they write, and the synth tool will only synthesise what you tell it to, and maintain the functionality you requested.

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hgomersall
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Registered: ‎12-27-2014
At an RTL level, they're identical. If you change the logic, something different might happen I agree, which would require the synthesis tool to do something different.

I don't understand your point. If I write `A = C or not(B and C)` I would expect that to be optimised to `A = True`, which definitely has timing implications.

You can't possibly expect the engineer to understand every detail of the implementation, otherwise every architectural change would require rewriting every bit of code. This is patently not the case anyway - the elaborated block diagram looks very different to the code I write.
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hgomersall
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Registered: ‎12-27-2014
The whole point of synthesis is to convert RTL into equivalent FPGA logic. It is by nature a conversion process that maps logic to logic. The truth of your RTL description is _all_ that matters, and that can be proved.
jmcclusk
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Registered: ‎02-24-2014

This is controlled by the synthesis option  "-resource_sharing" in Vivado.   The default value is "auto".   In general, if Vivado detects this kind of optimization, it will swap the order of the multiplexers and adders to minimize the logic.    Synplicity pioneered this optimization about 15 years ago. 

Don't forget to close a thread when possible by accepting a post as a solution.

View solution in original post

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hgomersall
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Registered: ‎12-27-2014

@jmccluskVery helpful, thank you!

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