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Explorer
Explorer
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Registered: ‎09-05-2015

Out of context module synthesis removed from Design run tab

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Hi,

 

le'ts say I have module

 

module top(input in_0, in_1,

                   output out_0, out_1);

 

    func_0 function_0(in_0, out_0);

    func_1 function_1(in_1, out_1);

 

endmodule

 

module  func_0 (input in_0,  output out_0);

    // empty

endmodule

 

module  func_1 (input in_1,  output out_1);

    // empty

endmodule

 

 

First, empty out the contents. Then, synthesize top, func_0 and func_1 out of context.

Then, read synthesized func_0 checkpoint and func_1 checkpoint from top checkpoint.

 

Here, do I need to re-run top-level synthesis once I read_checkpoint two func_0 and func_1 netlists, or

can I go to opt_design stage?

 

 

Thanks!

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Moderator
Moderator
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Registered: ‎09-15-2016

Re: Out of context module synthesis removed from Design run tab

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Hi @moon5756

 

In addition to @jmcclusk comments, if are you trying to use this synthesis checkpoint to open somewhere else then you can open the synthesized design and do write_checkpoint. This check point will read both ooc checkpoint along with top level checkpoint.

Now you can open this checkpoint and proceed to opt_design phase of impl.

 

Regards

Rohit

Regards
Rohit
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Mentor
Mentor
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Registered: ‎02-24-2014

Re: Out of context module synthesis removed from Design run tab

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you should be able to proceed to "opt_design" after reading in the out of context module checkpoints, provided that you've put black box attributes on the empty modules, so they aren't optimized away.   At least I think you need black box attributes...  it might actually work.   Let us know if they are needed.

Don't forget to close a thread when possible by accepting a post as a solution.
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Moderator
Moderator
821 Views
Registered: ‎09-15-2016

Re: Out of context module synthesis removed from Design run tab

Jump to solution

Hi @moon5756

 

In addition to @jmcclusk comments, if are you trying to use this synthesis checkpoint to open somewhere else then you can open the synthesized design and do write_checkpoint. This check point will read both ooc checkpoint along with top level checkpoint.

Now you can open this checkpoint and proceed to opt_design phase of impl.

 

Regards

Rohit

Regards
Rohit
----------------------------------------------------------------------------------------------
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Give Kudos to a post which you think is helpful and reply oriented.
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View solution in original post

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