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Voyager
Voyager
366 Views
Registered: ‎06-20-2017

Oversight in SystemVerilog synthesizer leads to less than optimal netlist

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Similar to this post, but for systemVerilog.

Hopefully our ever friendly Xilinx forum moderators are having a great day, and can get this to the appropriate engineer with XST responsibility. 

The following SystemVerilog code produces 157 LUTs and 129 registers (and does not meet high performance timing requirement).

 

  logic   signed [2*p_num_bits+1:0] my_logic;  
// ... 
          // inside clocked process
          if (my_logic >= 0) begin
            // difference is >= 0
            // do_this
          end
          else begin
            // difference is < 0
            // do_that        
          end          
          

But if I change it to:

 

 

  logic   signed [2*p_num_bits+1:0] my_logic;  
// ... 
          // inside clocked process
          if (my_logic < 0) begin
            // difference is < 0
            // do_that    
          end
          else begin
            // difference is >= 0
            // do_this
          end          

Then I get 133 LUTs and 129 registers (and meets high performance timing requirement specified in the first example)

 

There is no logical reason I can think of for the synthesizer to not recognize that only the sign bit differs.  The synthesizer figures this out in the second given example above, but not the first given example above.

Please submit a change request to the XST team.  I know it's not HLS or SDAccel, but revenue is still generated with plain old HDLs.

The first example above leads to timing closure problems in high performance designs, and will slow inexperienced users down.

Test was performed using Vivado 2019.1 with default synthesis and implementation settings.

Also mildly annoying, VHDL < 0 produces the smallest design.

 

+--------------------+---------+----------+----------------+
|                    |   LUTS  |   REGS   |  Meets Timing  |
+--------------------+---------+----------+----------------+
| VHDL < 0           |   133   |   129    |   Yes          |
+--------------------+---------+----------+----------------+
| VHDL >= 0          |   157   |   129    |   NO           |
+--------------------+---------+----------+----------------+
| SystemVerilog < 0  |   133   |   129    |   Yes          |
+--------------------+---------+----------+----------------+
| SystemVerilog >= 0 |   157   |   129    |   NO           |
+--------------------+---------+----------+----------------+

There are rumors floating around on this forum that if the issues isn't HLS or SystemVerilog, Xilinx moderators may not prioritize the issue.  My own experience is it seems to be challenging to get Xilinx's attention on such constructive feedback.

 

But the above table shows that the problem is independent of the language parser.

Also, I suspect similar subtle changes to C++ code would likely lead to the same sub-optimal time consuming difference in HLS as is illustrated in the above table.

In business terms this translates to:  Longer time to market, longer time to realized revenue (for all interested parties).

Please let me know when you file a change request.  Yes I have a work around but I'd like to know my time providing feedback isn't falling on deaf ears.

Thank you.

Mike
1 Solution

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Xilinx Employee
Xilinx Employee
220 Views
Registered: ‎07-21-2014

Re: Oversight in SystemVerilog synthesizer leads to less than optimal netlist

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Hi @maps-mpls 

 

MSB of signed input is sufficient while performing either of operations- "x >= 0" or "x < 0". However we are only optimizing this when using "x < 0" operation.

I have reported this issue for future improvement. 

 

-Shreyas

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2 Replies
Xilinx Employee
Xilinx Employee
253 Views
Registered: ‎07-21-2014

Re: Oversight in SystemVerilog synthesizer leads to less than optimal netlist

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Hi @maps-mpls 

 

Thanks for the valuable feedback.

I am looking into this issue and will create testcase to reproduce the scenario.

I will let you know the updates soon.

 

-Shreyas

----------------------------------------------------------------------------------------------
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Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
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Highlighted
Xilinx Employee
Xilinx Employee
221 Views
Registered: ‎07-21-2014

Re: Oversight in SystemVerilog synthesizer leads to less than optimal netlist

Jump to solution

Hi @maps-mpls 

 

MSB of signed input is sufficient while performing either of operations- "x >= 0" or "x < 0". However we are only optimizing this when using "x < 0" operation.

I have reported this issue for future improvement. 

 

-Shreyas

----------------------------------------------------------------------------------------------
Try to search answer for your issue in forums or xilinx user guides before you post a new thread.

Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
Give Kudos (star provided in right) to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post