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Visitor gabyxilca
Visitor
10,655 Views
Registered: ‎11-07-2010

PAR 1018 for a reset button??!!

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I am receiving a place and route error 1018 for a reset button. Place is thinking that this is a clock. How can do to tell it that this is a reset button?

 

I tried the CLOCK_DEDICATED_ROUTE = FALSE but gave a warnig but the download code on the board din't work. I want to understand what's happening?!

 

.........
ERROR:Place:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /
   clock site pair. The clock component <rst_IBUF_BUFG> is placed at site <BUFGMUX_X2Y0>. The IO component <rst> is
   placed at site <IPAD199>.  This will not allow the use of the fast path between the IO and the Clock buffer. If this
   sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf
   file to demote this message to a WARNING and allow your design to continue. However, the use of this override is
   highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be
   corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These
   examples can be used directly in the .ucf file to override this clock rule.
   < NET "rst" CLOCK_DEDICATED_ROUTE = FALSE; >

Here is the ucf file

...

ET "clk" LOC = "E12" |IOSTANDARD = LVCMOS33;
#NET "rst" LOC = "T15" | IOSTANDARD = "LVTTL" | PULLDOWN | CLOCK_DEDICATED_ROUTE = FALSE;
NET "rst" LOC = "T15" | IOSTANDARD = "LVTTL" | PULLDOWN;

...

I have a Spartan-3A Starter Kit Board

 

The code:

--------------------------------------------

 

 process(clk, rst)
  variable clk_count : integer := 0;
  variable waitCycles : integer := 100;  -- number of cycles to wait before
 begin
  if (rst = '1') then
   clk_count := 0;
  elsif(clk'event and clk = '1') then
   if (clk_count < waitCycles) then 
     clk_count := clk_count + 1;
     --show <= '1';
   else

...

 

---------------------------------------------------------

 process(clk, rst) 

 variable clk_count : integer := 0;
  
 begin
  if(rst = '1') then
   clk_count := 0;
   state <= powerOn;
   
   --waitCyclesSig <= wait15ms;
   --waitCycles <= wait40us;
   --nextTxState <= TxIdle;
   --next_TxState <= TxIdle;
  elsif(clk'event and clk = '1') then

...

 

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Xilinx Employee
Xilinx Employee
13,840 Views
Registered: ‎01-03-2008

Re: PAR 1018 for a reset button??!!

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> this is the code of the "case" part of the FSM

> ------------------------------------------------------------------------------------

>   process(state,rst)
>    begin

>      
>        if(rst = '1')then
>            waitCycles <= wait40us;
>            nextTxState <= TxIdle;
>        else

 

And this is where your code created latches and turned a reset net into clock.

 

Use the reset only in the clock/register  portion of your design.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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16 Replies
Instructor
Instructor
10,652 Views
Registered: ‎08-14-2007

Re: PAR 1018 for a reset button??!!

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It's not clear why rst would be a "clock" given the code snippets

you posted.  There may be clues in other sections of the code.

In any case you might want to look at the "technology schematic"

to see what your VHDL synthesized into.  Perhaps something

will jump out at you there...

 

-- Gabor

-- Gabor
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Xilinx Employee
Xilinx Employee
10,626 Views
Registered: ‎05-14-2008

Re: PAR 1018 for a reset button??!!

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Seems that the a BUFG is inserted on the rst signal while the rst pad is not a GC pad, which causes the problem. To remove the BUFG, add "buffer_type = ibuf" constraint to the rst signal. 

 

-Vivian

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Instructor
Instructor
10,618 Views
Registered: ‎08-14-2007

Re: PAR 1018 for a reset button??!!

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I understand about automatic clock buffer insertion by synthesis, but why

would a reset signal end up with a BUFG?  It seems to imply that the rst

signal has "clock" loads as it is interpreted by XST.  That's why I suggested

to look at the technology schematic.  Adding a buffer_type property might

fix the error, but doesn't explain the original cause.  And it could cover up some

other design problems such as unintentional latch creation.

 

-- Gabor

-- Gabor
Historian
Historian
10,611 Views
Registered: ‎02-25-2008

Re: PAR 1018 for a reset button??!!

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@gszakacs wrote:

I understand about automatic clock buffer insertion by synthesis, but why

would a reset signal end up with a BUFG?  It seems to imply that the rst

signal has "clock" loads as it is interpreted by XST.  That's why I suggested

to look at the technology schematic.  Adding a buffer_type property might

fix the error, but doesn't explain the original cause.  And it could cover up some

other design problems such as unintentional latch creation.

 

-- Gabor


 

I agree with Gabor -- there is no reason for the tools to insert a clock buffer on the reset signal, unless said reset signal is used somewhere in the design (that we can't see) as a clock.

 

So it's a design error, not a tools problem.

----------------------------Yes, I do this for a living.
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Visitor gabyxilca
Visitor
10,590 Views
Registered: ‎11-07-2010

Re: PAR 1018 for a reset button??!!

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OK guys thanks for the replies i will put some more details i think i can find a solution but i will post some more details to have some feedback to see why it's hapenning.

 

What i am trying to acomplish is an FSM. I have many component but the one that is causing the trouble is the iner most component the one that hold the FSM "case"

 

this is the code of the synchronous part of the FSM

------------------------------------------------------------------------------------

    process(clk, rst) --, data,show)
    variable clk_count : integer := 0;
        
    begin
        if(rst = '1') then
            clk_count := 0;
            state <= powerOn;
            
           elsif(clk'event and clk = '1') then
                if (clk_count = waitCycles) then    
                    clk_count := 0;                 
                    if (nextTxState = TxIdle) then
                        if (show = '1') and (state = idle) then
                            state <= write_char;
                        else
                            state <= nextState;
                        end if;
              
                    else
                        state <= nextTxState;
                    end if;

                else
                    clk_count := clk_count + 1;
                end if;
            end if;
    end process;

 

this is the code of the "case" part of the FSM

------------------------------------------------------------------------------------

    process(state,rst)
    begin
        
        if(rst = '1')then
            waitCycles <= wait40us;
            nextTxState <= TxIdle;
        else
                case state is
                    when powerOn =>

                                       ...

                end case;
            end if;
    end process;   

 

--------------------------------------------

Now when i remove the "rst" signal from the sensitivity list and from process of the "case" part , i will not get this error anymore, but if i keep the "rst" this error occur. so a process like this

 

------------------------------------------------------------------------------------

    process(state)
    begin
                case state is
                    when powerOn =>

                                       ...

                end case;
    end process;   

 

won't give such error (mean the PAR 1018 error).

What's happening?

 

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Xilinx Employee
Xilinx Employee
13,841 Views
Registered: ‎01-03-2008

Re: PAR 1018 for a reset button??!!

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> this is the code of the "case" part of the FSM

> ------------------------------------------------------------------------------------

>   process(state,rst)
>    begin

>      
>        if(rst = '1')then
>            waitCycles <= wait40us;
>            nextTxState <= TxIdle;
>        else

 

And this is where your code created latches and turned a reset net into clock.

 

Use the reset only in the clock/register  portion of your design.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Visitor gabyxilca
Visitor
10,583 Views
Registered: ‎11-07-2010

Re: PAR 1018 for a reset button??!!

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Thks for the answer

 

yes i tried into google and didn't find any answers.

 

What i want to know is why does it consider the "rst" as a clock if it was in the "case" part of the FSM although i am not using any rising_edge() or "if(rst'event and rst='1')" or any variation of that?

 

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Xilinx Employee
Xilinx Employee
10,580 Views
Registered: ‎01-03-2008

Re: PAR 1018 for a reset button??!!

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> yes i tried into google and didn't find any answers.

 

That is just part of my signature and wasn't directed at your post specifically.

 

> What i want to know is why does it consider the "rst" as a clock if it was in the "case" part of the FSM

 

A FSM is a descriptive construct it doesn't actually exist as a basic element.  What does exist as a basic element is a latch, as I said earlier, and that is what your code is creating.  A latch does not use rising_edge()  or 'event  (this will create a register or flip/flop element).  A latch will be generated any time that HDL code describes a saved state as yours does.  In this case the Gate (aka clock)  input of the latch is driven by your  "rst" net.

 

Check the synthesis report file you will see that you have latches.  Latches should only be present in a design in special circumstances and if they turn up in your design when you did not intend them to be there it means that your code is incorrect.

 

Only use the reset in the same process as your rising_edge() and you won't have any problems.  You will have even less problems if you use synchronous resets instead of the asynchronous reset that you are currently coding.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
Visitor gabyxilca
Visitor
10,552 Views
Registered: ‎11-07-2010

Re: PAR 1018 for a reset button??!!

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Thx very much for the reply

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Historian
Historian
6,734 Views
Registered: ‎02-25-2008

Re: PAR 1018 for a reset button??!!

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@gabyxilca wrote:

Thks for the answer

 

yes i tried into google and didn't find any answers.

 

What i want to know is why does it consider the "rst" as a clock if it was in the "case" part of the FSM although i am not using any rising_edge() or "if(rst'event and rst='1')" or any variation of that?

 


Well, in addition to what Ed McGettigan has noted, you're YET ANOTHER VICTIM of the two-process state-machine methodology.
Write the state machine as one synchronous process, and these problems will tend to go away.

 

----------------------------Yes, I do this for a living.
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Visitor gabyxilca
Visitor
6,731 Views
Registered: ‎11-07-2010

Re: PAR 1018 for a reset button??!!

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This is what I was doing before, but i saw the majority of designer and practicly all the book use and recomend the 2 processes FSM, so I got influenced by them and start doing the 2 processes FSM!! I think i need to test both and compare results to convience my self

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Instructor
Instructor
6,729 Views
Registered: ‎08-14-2007

Re: PAR 1018 for a reset button??!!

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@gabyxilca wrote:

This is what I was doing before, but i saw the majority of designer and practicly all the book use and recomend the 2 processes FSM, so I got influenced by them and start doing the 2 processes FSM!! I think i need to test both and compare results to convience my self


 

Burn those books.

 

Save yourself headaches and get used to writing FSM's as a single

synchronous process.  If you must use two processes, at least learn

to write combinatorial processes that don't create latches.  I'm sure

the book examples have proper sensitivity lists and assign all

outputs in each case, or give them all a default value before

falling into the case statement.

 

-- Gabor

-- Gabor
Historian
Historian
6,721 Views
Registered: ‎02-25-2008

Re: PAR 1018 for a reset button??!!

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@gabyxilca wrote:

This is what I was doing before, but i saw the majority of designer and practicly all the book use and recomend the 2 processes FSM,


 

Dunno where you saw this, but the first statement ("the majority of designers ...") is not true.

 

The aging textbooks recommend the two-process state machine because they haven't been updated in 20 years. Back in the dark ages, synthesis tools were unable to recognize a state machine coded using one synchronous state machine. But any modern synthesis tool understands how to do this, and except in very specific circumstances the one-synchronous-process state machine template is what you should use.

----------------------------Yes, I do this for a living.
Visitor gabyxilca
Visitor
6,719 Views
Registered: ‎11-07-2010

Re: PAR 1018 for a reset button??!!

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Yes i am aware about the "not giving each signal in every state a value will create a latch" and i think this is clear to everyone. What wasn't clear is how athe "rst" end up being the "clock" of the latch. After the clarification given previously, I understood that because there wasn't any other input to the process sensitivity list beside "state" and "rst" the synthesis, tool choose the "rst" signal as the input clock for the latch which confused place and route, although it could have chosen the "state" signal instead which never occured since the syntesizer recognized this is a FSM and the "state" is the state signal.

 

For the FSM with double process subject , if i had used the single process way of coding, i think this error would have never occured (but the latch creation would have been passed unnoticed unless you look at the synthesis report and see the latches created). If it don't consume more resources (any type) i think i will stick for the double process FSM since it make your code look clearer. Unless someone tell me that there are advantages to use a single process FSM is better then the double process I don't see why we don't stick with it specially for complex FSMs

 

Also about the statment "the majority of designers..." wasn't that a general statment. what was meant was "the majority of designers i knew". Again am not a VHDL guru and my experience is limited. You may have more experience then me, which is very good and am very thankful that you share your point of view and your experience with the rest of us.

 

Thanks for all

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Instructor
Instructor
6,696 Views
Registered: ‎08-14-2007

Re: PAR 1018 for a reset button??!!

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For the FSM with double process subject , if i had used the single process way of coding, i think this error would have never occured (but the latch creation would have been passed unnoticed unless you look at the synthesis report and see the latches created). If it don't consume more resources (any type) i think i will stick for the double process FSM since it make your code look clearer. Unless someone tell me that there are advantages to use a single process FSM is better then the double process I don't see why we don't stick with it specially for complex FSMs

 

If your only process is synchronous, then there is no latch creation.  Period.  This

alone would be a good reason to use the single process FSM, especially for

complex FSM's.

 

I personally fail to see how using two processes makes an FSM more readable.  I

generally consider having all of the information in one place more readable than

having to scroll back and forth to see which of the many signals in the

combinatorial process are registered before they leave the FSM for exernal use.

 

Just my 2 cents,

Gabor

-- Gabor
Scholar ronnywebers
Scholar
2,100 Views
Registered: ‎10-10-2014

Re: PAR 1018 for a reset button??!!

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@gszakacs@bassman59, you just convinced me to forget about 2 process or even 3 process FSM's, and move to single process FSM's. I did run into the same latch issues in the past as many other people do.

 

I have a dozen of VHDL books (all relevant ones), and as far as I remember none of them uses a single process FMS.

 

I think the reason for this are the schematics that are used to represent Moore and Mealy state machines, these contain 2 or 3 blocks ...

 

I recently bought a book that only deals with FSM's : 'Finite state machines in hardware' by Pedroni, MIT Press, 2013'.  I was hoping to become an expert in FSMs, as I need some more complicated FSM's with timers / counters in it, etc. The book does deal with this, but unfortunately it uses 2 or 3 process approaches... so I can about throw it away now - or burn it as @gszakacs says :-)

 

Also Peter Ashenden's book, which is one of 'the' standards for VHDL says in chapter 21 : The preferred style is to separate the implementation into two processes, one describing the combinational logic that calculates the next state and output values, and the other being a register that stores the state.

 

So still, I am convinced about your motivation to use single process FSM's, but I don't get it why all these books (2013 is quiet recent...) keep on promoting 2/3 process FSMs....

 

Vivado UG901 (synthesis) gives a short example of a single process FSM, but without much explanation. 

 

Wouldn't it be a great idea for a company like Xilinx to either write a more detailed 'HDL Coding practice' manual, instead of treating it in a few pages? Some more advanced examples, like using counters (typically used in uart, spi, ... implementations etc) would be welcome. 

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