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Anonymous
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Partial input delay

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I have some trouble with a design that I need to implement into the Aritx 7 EVB. 

 

I have added some timing contraints to the design for the clocks and also for the 

 

input ports: 

set_input_delay -clock CLK -min 1.000 PORT_IN

 

well as 

 

output ports: 

 

set_output_delay -clock CLK -max 1.000 PORT_OUT

But now I see partial input/output delays in the timing report. 

 

It comes up in the Check timing window. It is same amount of ports that I have in there. 

 

I am using an Artix 7 200T FPGA. 

 

Help would be greatly appreciated.

 

Thx

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Guide
Guide
7,687 Views
Registered: ‎01-23-2009

Re: Partial input delay

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You need to specify both a -min and a -max for both input and output delays.

 

Your current constraints specify a min only for input (which leaves the max unconstrained, hence a partial input delay). Similarly, for the output delay, you have only a max, which leaves the min unconstrained.

 

Avrum

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Highlighted
Guide
Guide
7,688 Views
Registered: ‎01-23-2009

Re: Partial input delay

Jump to solution

You need to specify both a -min and a -max for both input and output delays.

 

Your current constraints specify a min only for input (which leaves the max unconstrained, hence a partial input delay). Similarly, for the output delay, you have only a max, which leaves the min unconstrained.

 

Avrum

View solution in original post

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Anonymous
Not applicable
4,370 Views

Re: Partial input delay

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Thanks Avrum
That was very helpful.
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