I am new in FPGA designing and started with some test-projects.
First project i made, was a simple SPI interface and a 16x8 ram, where i can write and read data.
Everything worked fine, in post-route simulation and in system.
2nd step was to try out the same but with a IP core (distributed memory generator).
This time post-route simulation worked also fine, but in system I read the whole time wrong data and I have no idea what the problems could be.
Could u say me, what for sources of trouble are possible?
Thanks a lot.