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Participant
Participant
805 Views
Registered: ‎01-01-2019

Post synthesis simulation is mismatch with behavioral simulation

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Hi All,

I have writen a simple code to simulate the behavior of a memory.

It works fine in behavioral simulation and synthesis goes well.

But in post synthesis simulation, its behavior is strange and internal registers(like address_reg ) don't update at all.

The code is as bellow, I hope you can help me.


module FlashEmulator(
input ALE,
input nWE,
input nRE,
input CLE,
inout [7:0] DQ,
output reg nRB =1
);
reg [7:0] address_reg;
reg [7:0] command_reg;
reg [7:0] status_reg;
reg [7:0] memory [255:0];
reg[7:0] DQ_reg;
reg signalling = 1'b0;

reg signalOut = 1'b1;


assign DQ = DQ_reg;

always @(posedge signalling)
begin
nRB = 1;
signalling = 0;
end

always @(posedge nRE)
begin
DQ_reg = 8'bzzzzzzzz;
end

always @(negedge nRE)
begin
DQ_reg = memory[address_reg];
nRB = 0;
signalling = 1;
end




always @(posedge nWE)
begin
if (CLE == 1)
begin
command_reg = DQ;
nRB = 0;
signalling = 1;
end // for if
else // CLE is 0 , so there is no command. It will be write data or address
begin
command_reg = command_reg;
if (ALE == 1)
begin
address_reg = DQ;
nRB = 0;
signalling = 1;
end
else // ALE was 0 so it is a data write
begin
address_reg = address_reg;
memory[address_reg] = DQ;
nRB = 0;
signalling = 1;
end

end // for else
end // for always

endmodule

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Xilinx Employee
Xilinx Employee
729 Views
Registered: ‎05-22-2018

Hi mostafa@sint ,

For understanding what changes has occured post synthesis which leads to mismatch in Behavioral and Post synthesis Simulation, you can have a good idea by comparing the Elaborated design and Synthesized schematic.

Also you can check for Synthesis log files for Warnings and Critical Warnings.

Thanks,

Raj

View solution in original post

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6 Replies
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Scholar
Scholar
780 Views
Registered: ‎08-01-2012

You are using logic signals like clocks? why are yo not using a clock?

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Teacher
Teacher
760 Views
Registered: ‎06-16-2013

Hi mostafa@sint 

 

Because your design is asynchronous logic. So, when you do post simulation, the result between logical simulation and post simulation are defferent.

 

I suggest you to choose clock synchronous logic with some clocks.

 

Best regards,

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Guide
Guide
739 Views
Registered: ‎01-23-2009

You need to understand the difference between RTL and HDL. HDL, a Hardware Description Language (like Verilog) is a computer language that has the capability to describe hardware systems - most notably mechanisms for modelling the passage of simulated time. RTL, is Register Transfer Language - this is a subset of an RTL that a synthesis tool can convert from code to a real hardware implementation. In other words the synthesis tool analyzes the behavior described by a piece of RTL code and infers the equivalent real hardware cells that perform that function.

Let's take a look at just one part of your code:

always @(posedge signalling)
begin
...
signalling = 0;
end

This describes a piece of hardware that, when it detects the rising edge of a given signal, it forces that signal back to 0. Exactly what real hardware cell (or combination of real hardware cells) can do this? The answer is "none" - there simply is no such thing.

I am surprised that the synthesis tool didn't issue an error on this code - it is clearly not synthesizable. Given that, I have no idea what (essentially meaningless) hardware it constructed to replace this RTL snippet...

So ultimately... Your code is not synthesizable RTL. Furthermore, what you are trying to do (emulate an old style asynchronous SRAM interface) is not something that can (or at least should) be implemented in an FPGA; FPGAs are designed for synchronous logic - even assuming the grossly non-synthesizable stuff was removed/replaced in your code, this would still not be something you should try an implement in an FPGA.

You need to go back to the books and learn what synchronous digital design looks like and then learn how to write RTL code that implements the synchronous systems you are trying to create.

Avrum

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Xilinx Employee
Xilinx Employee
730 Views
Registered: ‎05-22-2018

Hi mostafa@sint ,

For understanding what changes has occured post synthesis which leads to mismatch in Behavioral and Post synthesis Simulation, you can have a good idea by comparing the Elaborated design and Synthesized schematic.

Also you can check for Synthesis log files for Warnings and Critical Warnings.

Thanks,

Raj

View solution in original post

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Participant
Participant
715 Views
Registered: ‎01-01-2019

Hi  rshekhaw

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Participant
Participant
712 Views
Registered: ‎01-01-2019

Just for your information, the cod is definitely a synthesizable RTL.

And the problem was exactly here that it was synthesized but didn't work as you expect from it.

 

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